• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.145-150
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• 2013

This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1465-1470
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• 2017

In conventional MOSFETs, the silicon thickness is always larger than inversion layer, so that the drain induced barrier lowering (DIBL) is expressed as a function of oxide thickness and channel length regardless of silicon thickness. However, since the silicon thickness is fully depleted in the sub-10 nm low doped double gate (DG) MOSFET, the conventional SPICE model for DIBL is no longer available. Therefore, we propose a novel DIBL SPICE model for DGMOSFETs. In order to analyze this, a thermionic emission and the tunneling current was obtained by the potential and WKB approximation. As a result, it was found that the DIBL was proportional to the sum of the top and bottom oxide thicknesses and the square of the silicon thickness, and inversely proportional to the third power of the channel length. Particularly, static feedback coefficient of SPICE parameter can be used between 1 and 2 as a reasonable parameter.

• Wind and Structures
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• v.31 no.3
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• pp.185-196
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• 2020

A method to reduce the wind pressure at the leading edge of a noise barrier was investigated by gradually lowering the height of a member added to the end of the noise barrier. The shape of the lowered height of the added member was defined by its length and slope, and the optimal variable was determined in wind tunnel testing via the boundary-layer wind profile. The goal of the optimal shape was to reduce the wind pressure at the leading edge of the noise barrier to the level suggested in the Eurocode and to maintain the base-bending moment of the added member at the same level as the noise-barrier section. Using parametric wind tunnel investigation, an added member with a slope of 1:2 that protruded 1.2 times the height of the noise barrier was proposed. This added member is expected to simplify, or at least minimize, the types of column members required to equidistantly support both added members and noise barriers, which should thereby improve the safety and construction convenience of noise-barrier structures.

• Journal of Sensor Science and Technology
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• v.26 no.2
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• pp.79-84
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• 2017

The drain current of the SB MOSFET was analytically modeled by an equation composed of thermionic emission and tunneling with consideration of the image force lowering. The depletion region electron concentration was used to model the channel electron concentration for the tunneling current. The Schottky barrier width is dependent on the channel electron concentration. The drain current is changed by the gate oxide thickness and Schottky barrier height, but it is hardly changed by the doping concentration. For a GaN SB MOSFET with ITO source and drain electrodes, the calculated threshold voltage was 3.5 V which was similar to the measured value of 3.75 V and the calculated drain current was 1.2 times higher than the measured.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.329-333
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• 2013

SiOC films were prepared by capacitively coupled plasma chemical vapor deposition, and the correlation between the binding energy by X-ray photoelectron spectroscopy and Arrhenius equation for ionization energy was studied. The ionization energy decreased with increase of the potential barrier, and then the dielectric constant also decreased. The binding energy decreased with increase of the potential barrier. The dielectric constant and electrical characteristic of SiOC film was obtained by Arrhenius equation. The dielectric constant of SiOC film was decreased by lowering the polarization, which was made from the recombination between opposite polar sites, and the dissociation energy during the deposition. The SiOC film with the lowest dielectric constant had a flat surface, which depended on how carbocations recombined with other broken bonds of precursor molecules, and it became a fine cross-linked structure with low ionization energy, which contributed to decreasing the binding energy by Si 2p, C 1s electron orbital spectra and O 1s electron orbital spectra. The dielectric constant after annealing decreased, owing to the extraction of the $H_2O$ group, and lowering of the polarity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.287-298
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• 2007

A two-dimensional treatment of the potential distribution under the depletion approximation is presented for poly-crystalline silicon thin film transistors. Green's function approach is adopted to solve the two-dimensional Poisson's equation. The solution for the potential distribution is derived using Neumann's boundary condition at the silicon-silicon di-oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain-boundaries. Also short-channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.173-181
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• 2005

A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.2
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• pp.104-109
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• 2019

An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.