• Title/Summary/Keyword: Barrier film

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Prevention of thin film failures for 5.0-inch TFT arrays on plastic substrates

  • Seo, Jong-Hyun;Jeon, Hyung-Il;Nikulin, Ivan;Lee, Woo-Jae;Rho, Soo-Guy;Hong, Wang-Su;Kim, Sang-Il;Hong, Munpyo;Chung, Kyuha
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.700-702
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    • 2005
  • A 5.0-inch transmissive type plastic TFT arrays were successfully fabricated on a plastic substrate at the resolution of $400{\times}3{\times}300$ lines (100ppi). All of the TFT processes were carried out below $150^{\circ}C$ on PES plastic films. After thin film deposition using PECVD, thin film failures such as film delamination and cracking often occurred. For successful growth of thin films (about 1um) without their failures, it is necessary to solve the critical problem related to the internal compressive stress (some GPa) leading to delamination at a threshold thickness value of the films. The Griffith's theory explains the failure process by looking at the excess of elastic energy inside the film, which overcomes the cohesive energy between film and substrate. To increase the above mentioned threshold thickness value there are two possibilities: (i) the improvement of the interface adhesion (for example, through surface micro-roughening and/or surface activation), and (ii) the reduction of the internal stress. In this work, reducing a-Si layer film thickness and optimizing a barrier SiNx layer have produced stable CVD films at 150oC, over PES substrates

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Low-temperature crystallization of high-dielectric (Ba,Sr)$TiO_3$ thin films for embedded capacitors

  • Cho, Kwang-Hwan;Kang, Min-Gyu;Kang, Chong-Yun;Yoon, Seok-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.03a
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    • pp.21-21
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    • 2010
  • (Ba,Sr)$TiO_3$ (BST) thin film with a perovskite structure has potential for the practical application in various functional devices such as nonvolatile-memory components, capacitor, gate insulator of thin-film transistors, and electro-optic devices for display. Normally, the BST thin films derived from sol-gel and sputtering are amorphous or partially crystalline when processed below $600^{\circ}C$. For the purpose of integrating BST thin film directly into a Si-based read-out integrated circuit (ROIC), it is necessary to process the BST film below $400^{\circ}C$. The microstructural and electrical properties of low-temperature crystallized BST film were studied. The BST thin films have been fabricated at $350^{\circ}C$ by UV-assisted rapidly thermal annealing (RTA). The BST films are in a single perovskite phase and have well-defined electrical properties such as high dielectric constant, low dielectric loss, low leakage current density, and high breakdown voltage. Photoexcitation of the organics contained in the sol-gel-derived films by high-intensity UV irradiation facilitates elimination of the organics and formation of the single-crystalline phase films at low temperatures. The amorphous BST thin film was transformed to a highly (h00)-oriented perovskite structure by high oxygen pressure processing (HOPP) at as low as $350^{\circ}C$. The dielectric properties of BST film were comparable to (or even better than) those of the conventionally processed BST films prepared by sputtering or post-annealing at temperature above $600^{\circ}C$. When external pressure was applied to the well-known contractive BST system during annealing, the nucleation energy barrier was reduced; correspondingly, the crystallization temperature decreased. The UV-assisted RTA and HOPP, as compatible with existing MOS technology, let the BST films be integrated into radio-frequency circuit and mixed-signal integrated circuit below the critical temperature of $400^{\circ}C$.

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Structural and electrical characteristics of IZO thin films with deposition temperature (증착 온도에 따른 IZO 박막의 구조적 및 전기적 특성)

  • Jun, D.G.;Lee, Y.L.;Lee, K.M.
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.3
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    • pp.67-74
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    • 2011
  • In this study, we have investigated the effect of the substrate temperature on the structural and the electrical characteristics of IZO thin films for the OLED (organic light emitting diodes) devices. For this purpose, IZO thin films were deposited by RF magnetron sputtering under various substrate temperature. The substrate temperature has been changed from room temperature to $400^{\circ}C$. Samples which were deposited under $250^{\circ}C$ show amorphous structure. The electrical resistivity of crystalline-IZO (c-IZO) film was higher than that of amorphous-IZO (a-IZO) film. And the electrical resistivity showed minimum value near $150^{\circ}C$ of deposition temperature. The OLED device was fabricated with different IZO substrates made by configuration of IZO/$\acute{a}$-NPD/DPVB/$Alq_3$/LiF/Al to elucidate the performance of IZO substrate. OLED devices with the amorphous-IZO (a-IZO) anode film show better current density-voltage-luminance characteristics than that of OLED devices with the commercial crystalline-ITO (c-ITO) anode film. It can be explained that very flat surface roughness and high work function of a-IZO anode film lead to more efficient hole injection by reduction of interface barrier height between anode and organic layers. This suggests that a-IZO film is a promising anode materials substituting conventional c-ITO anode in OLED devices.

IETS of Au/Polyimide/1-layer organic film /Pb Structures (Au/Polyimide/유기 단분자막/Pb 구조의 IETS)

  • ;;;M.I wamoto
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1995.05a
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    • pp.230-233
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    • 1995
  • Using Polyimide Langmuir-Blodgett(LB) films as a tunneling barrier, Current -Voltage(I-V) characteristics and inelastic electron tunneling spectroscoupy(IETS) of the junctions incorporating 1-layer orgainc monolayer were invesgated. Several peaks originating in vibrational modes of constituted molecules of 1-layer monolayers were clearly observed in the IET spectra.

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Electrical characteristics of p-PEDOT/n-GZO heterojunction (p-PEDOT/n-GZO heterojunction의 전기적 특성)

  • Lee, Jae-Sang;Park, Dong-Hoon;Koo, Sang-Mo;Lee, Sang-Yeol
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1332_1333
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    • 2009
  • The electrical properties of an inorganic/organic heterojunction has been investigated by spin coating the p-type polymer poly(3,4 ethylenedioxythiophene) : poly(styrenesulfonate) (PEDOT:PSS) on an n-type gallium doping zinc oxide (GZO) film. Current-voltage (I-V) characteristics of the fabricated heterojunction diodes have a good rectifying characteristics. The barrier height is calculated 0.8 eV.

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Plastic Substrate for Flexible Display

  • Kim, In-Sun;Hwang, Hee-Nam;Choi, Jae-Moon;Yeom, Eun-Hee;Park, Yong-Ho
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.995-997
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    • 2005
  • A plastic substrate for flexible display is developed. The gas barrier and optical properties of the substrate is improved through depositing silicon oxide/nitride layer and coating polymer layer on plastic film by sputtering process and wet coating process. Roll to roll processes will guarantee the productivity in the whole production process of the plastic substrate.

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Carrier Trap Characteristics varying with insulator thickness of MIS device (MIS소자의 절연막 두께 변화에 따른 캐리어 트랩 특성)

  • 정양희
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.800-803
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    • 2002
  • The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

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Aluminum Thin Film Capacitor Using Micro Pore Patterning and Electroless Ni-P plating

  • Lee, Chang-Hyeong;Zhang, Jingjing;Kim, Tae-Yu;Seo, Su-Jeong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2011.05a
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    • pp.113-113
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    • 2011
  • 알루미늄 박막 커패시터 제작을 위해 선택적인 알루미늄 etching과 anodizing을 이용한 유전체($Al_2O_3$) 형성, 전극층 형성을 위한 무전해 Ni-P 도금을 진행하였다. $5{\mu}m$ patterns/$10{\mu}m$ space를 가지는 dot patterns을 알루미늄 기판에 patterning하고, 이를 각각의 전류밀도 조건에서 etching한 후, barrier type anodizing을 진행하였다. 유전체에 전극층은 무전해 Ni-P 도금을 통해 형성하였으며, 이렇게 제작된 알루미늄 박막 커패시터 특성을 평가하였다.

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