• Title/Summary/Keyword: Ball grid array

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Development of the Copper Core Balls Electroplated with the Solder of Sn-Ag-Cu

  • Imae, Shinya;Sugitani, Yuji;Nishida, Motonori;kajita, Osamu;Takeuchi, Takao
    • Proceedings of the Korean Powder Metallurgy Institute Conference
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    • 2006.09b
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    • pp.1207-1208
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    • 2006
  • We developed the copper core ball electroplated with Sn-Ag-Cu of the eutectic composition which used mostly as Pb free solder ball with high reliability. In order to search for the practicality of this developed copper core ball, the evaluation was executed by measuring the initial joint strength of the sample mounted on the substrate and reflowed and by measuring the joint strength of the sample after the high temperature leaving test and the constant temperature and the humidity leaving test. This evaluation was compered with those of the usual other copper core balls electroplated with (Sn,Sn-Ag,Sn-Cu,Sn-Bi) and the Sn-Ag-Cu solder ball.

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Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

  • Tan, Fern-Nee;Lee, Sheng Chyan
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.69-74
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    • 2013
  • In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

Experimental Assessment of PBGA Packaging Reliability under Strong Random Vibrations (강력한 임의진동 하에서 PBGA 패키지의 실험적 신뢰성 검증)

  • Kim, Yeong K.;Hwang, Dosoon
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.3
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    • pp.59-62
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    • 2013
  • Experimental analyses on the solder joint reliability of plastic ball grid array under harsh random vibration were presented. The chips were assembled on the daisy chained circuit boards for the test samples preparation, half of which were processed for underfill to investigate the underfill effects on the solder failures. Acceptance and qualification levels were applied for the solder failure tests, and the overall controlled RMS of the power spectrum densities of the steps were 22.7 Grms and 32.1 Grms, respectively. It was found that the samples survived without any solder failure during the tests, demonstrating the robustness of the packaging structure for potential avionics and space applications.

Effects of Underfills on the Dynamic Bending Reliability of Ball Grid Array Board Assembly (Ball Grid Array 보드 어셈블리의 동적굽힘 신뢰성에 미치는 언더필의 영향)

  • Jang, Jae-Won;Bang, Jung-Hwan;Yoo, Se-Hoon;Kim, Mok-Soon;Kim, Jun-Ki
    • Korean Journal of Materials Research
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    • v.21 no.12
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    • pp.650-654
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    • 2011
  • In this paper, the effects of conventional and newly developed elastomer modified underfill materials on the mechanical shock reliability of BGA board assembly were studied for application in mobile electronics. The mechanical shock reliability was evaluated through a three point dynamic bending test proposed by Motorola. The thermal properties of the underfills were measured by a DSC machine. Through the DSC results, the curing condition of the underfills was selected. Two types of underfills showed similar curing behavior. During the dynamic bending reliability test, the strain of the PCB was step increased from 0.2% to 1.5% until the failure circuit was detected at a 50 kHz sampling rate. The dynamic bending reliability of BGA board assembly using elastomer modified underfill was found to be superior to that of conventional underfill. From mechanical and microstructure analyses, the disturbance of crack propagation by the presence of submicron elastomer particles was considered to be mainly responsible for that result rather than the shear strength or elastic modulus of underfill joint.

Effect of Surface Finish on Mechanical and Electrical Properties of Sn-3.5Ag Ball Grid Array (BGA) Solder Joint with Multiple Reflow (Sn-3.5Ag BGA 패키지의 기계적·전기적 특성에 미치는 PCB표면 처리)

  • Sung, Ji-Yoon;Pyo, Sung-Eun;Koo, Ja-Myeong;Yoon, Jeong-Won;Shin, Young-Eui;Jung, Seung-Boo
    • Korean Journal of Metals and Materials
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    • v.47 no.4
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    • pp.261-266
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    • 2009
  • The mechanical and electrical properties of ball grid array (BGA) solder joints were measured, consisting of Sn-3.5Ag, with organic solderability preservative (OSP)-finished Cu pads and Electroless Nickel/Immersion Gold (ENIG) surface finishes. The mechanical properties were measured by die shear test. When ENIG PCB was upper joint and OSP PCB was lower joint, the highest shear force showed at the third reflow. When OSP PCB was upper joint and ENIG PCB was lower joint, the highest shear force showed at the forth reflow. For both joints, after the die shear results reached the highest shear force, shear force decreased as a function of increasing reflow number. Electrical property of the solder joint decreased with the function of increasing reflow number. The scanning electron microscope results show that the IMC thickness at the bonding interface gets thicker while the number of reflow increases.

The Development of 2-Dimensional Inspection Algorithm using Camera for BGA device (카메라를 이용한 BGA 소자의 2차원 결함검출 알고리즘 개발)

  • Kim, Kee-Soon;Kim, Joon-Seek;Joo, Hyo-Nam
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2005.05a
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    • pp.437-442
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    • 2005
  • In this paper, we proposed the 2-dimensional inspection algorithm for micro-BGA(Ball Grid Array) device using a vision system. The proposed method uses the subpixel algorithm for high precision. The proposed algorithm preferentially extracts the package area of device in the input image. After the extraction of package area, each ball areas are extracted by ball search window method. The parameters for inspection are calculated for the extracted ball area. In the simulation results, we have the average error within $17{\mu}m$.

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Evaluation of Thermal Deformation Model for BGA Packages Using Moire Interferometry

  • Joo, Jinwon;Cho, Seungmin
    • Journal of Mechanical Science and Technology
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    • v.18 no.2
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    • pp.230-239
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    • 2004
  • A compact model approach of a network of spring elements for elastic loading is presented for the thermal deformation analysis of BGA package assembly. High-sensitivity moire interferometry is applied to evaluate and calibrated the model quantitatively. Two ball grid array (BGA) package assemblies are employed for moire experiments. For a package assembly with a small global bending, the spring model can predict the boundary conditions of the critical solder ball excellently well. For a package assembly with a large global bending, however, the relative displacements determined by spring model agree well with that by experiment after accounting for the rigid-body rotation. The shear strain results of the FEM with the input from the calibrated compact spring model agree reasonably well with the experimental data. The results imply that the combined approach of the compact spring model and the local FE analysis is an effective way to predict strains and stresses and to determine solder damage of the critical solder ball.

3-Dimensional Micro Solder Ball Inspection Using LED Reflection Image

  • Kim, Jee Hong
    • International journal of advanced smart convergence
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    • v.8 no.3
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    • pp.39-45
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    • 2019
  • This paper presents an optical technique for the three-dimensional (3D) shape inspection of micro solder balls used in ball-grid array (BGA) packaging. The proposed technique uses an optical source composed of spatially arranged light-emitting diodes (LEDs) and the results are derived based on the specular reflection characteristics of the micro solder balls for BGA A vision system comprising a camera and LEDs is designed to capture the reflected images of multiple solder balls arranged arbitrarily on a tray and the locations of the LED point-light-source reflections in each ball are determined via image processing, for shape inspection. The proposed methodology aims to determine the presence of defects in 3D BGA shape using the statistical information of the relative positions of multiple BGA balls, which are included in the image. The presence of the BGA balls with large deviations in relative position imply the inconsistencies in their shape. Experiments were conducted to verify that the proposed method could be applied to inspection without sophisticated mechanism and productivity problem.

BGA to CSP to Flip Chip-Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Journal of the Microelectronics and Packaging Society
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    • v.8 no.2
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    • pp.37-42
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    • 2001
  • The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.04a
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    • pp.27-34
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    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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