• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.10-15
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• 2016

In this paper, novel ball grid array (BGA) interconnection process using solderable anisotropic conductive adhesives (SACAs) with low-melting-point alloy (LMPA) fillers have been developed to enhance the processability in the conventional capillary underfill technique and to overcome the limitations in the no-flow underfill technique. To confirm the feasibility of the proposed technique, BGA interconnection test was performed using two types of SACA with different LMPA concentration (0 and 4 vol%). After the interconnection process, the interconnection characteristics such as morphology of conduction path and electrical properties of BGA assemblies were inspected and compared. The results indicated that BGA assemblies using SACA without LMPA fillers showed weak conduction path formation such as solder bump loss or short circuit formation because of the expansion of air bubbles within the interconnection area due to the relatively high reflow peak temperature. Meanwhile, assemblies using SACA with 4 vol% LMPAs showed stable metallurgical interconnection formation and electrical resistance due to the favorable selective wetting behavior of molten LMPAs for the solder bump and Cu metallization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.243-250
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• 2001

This paper presents the structure of a $\mu$Spring package, its fabrication process and an analysis of its electrical characteristics compared to that of a $\mu$BGA. It was found that both $\mu$BGA and $\mu$Spring packages provide with outstanding high speed signal transmission characteristics due to their lower inductance of package interconnection lines, smaller than half of inductance of TSOP package lines. Even the worst case substrate trace of a Rambus DRAM $\mu$Spring package yields the line inductance of 2.9nH, which provides with 25% margin compared to the Rambus DRAM specification of 4nH. The fabrication cost of $\mu$Spring package is lower than that of $\mu$BGA by 50%, passes 1000 thermal cycles, meets JEDEC Level 1 specification whereas $\mu$BGA does not, and thereby yields high reliability and strong competing power.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.25-31
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• 2010

In this study, we investigated the morphology and thermal stability of interfacial phases in joint between lead free solder(Sn-3.0Ag-0.5Cu) and electroless Ni-W-P under bump metallizations(UBM) with different tungsten contents as a function of thermal aging. Content of phosphorus of each deposits was fixed at 8 wt.%, and content of tungsten was variated each 0, 3, 6 and 9 wt.%. Specimens were prepared by reflowing at $255^{\circ}C$, aging range was $200^{\circ}C$ and up to 2 weeks. After reflow process, in the electroless Ni(W)-P/solder joint, the interfacial intermetallic compound(IMC) was showed both $(Cu,Ni)_6Sn_5$ and $(Ni,Cu)_3Sn_4$. UBM and generated IMC at the interface of lead free solder was proportionally increased with aging time. The thickness of IMC was increased because the generation rate of $Ni(W)_3P$ decreased with increasing contents of W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.27-33
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• 2008

With increasing use of portable appliances such as PDA and cellular phone, changing environment of applications requires higher solder joint reliability. The ENIG (Electroless Nickel Immersion Gold) process has been widely used for fine pitch SMT (Surface Mount Technology) and BGA (Ball Grid Array) packaged devices due to its benefits including excellent solderability, high uniformity and substantial legibility throughout the packaging process. Its brittle fracture of solder, however, has received increasingly attentions. It was Down that fracture brittleness is mainly related with black pad resulting from galvanic nickel corrosion and P-enriched layer formation between the IMC (Intermetallic Compounds) and electroless nickel layer. Theoretically, smooth electroless Ni layer was blown to have a advantages in minimizing the black pad phenomenon by uniform solution exchange during immersion gold plating. Nevertheless, how to control the surface morphology of electroless Ni layer has been hardly blown. This study investigates an effect of surface morphology of Cu underlayer on surface morphology of electroless Ni layer. To obtain various kinds of surface morphology of Cu layer, two types of Cu etching chemical and a number of Cu etching treatment were applied.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.37-42
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• 2001

The concerns of the toxicity and health hazard of lead in solders have demanded the research to find suitable lead-free solder alloys. It was discussed that effect of the intermetallic formation and structure on the reliability of solder joints. In this study, lead-free solder alloys with compositions of Sn/3.5Ag/0.75Cu, Sn/2.0Ag/0.5Cu/2.0Bi were applied to the 48 $\mu$BGA packages. Also, the lead-free solder alloys compared with eutectic Sn/37Pb solder using shear test under various aging temperature. Common $\mu$BGA with solder components was aged at $130^{\circ}C$, $150^{\circ}C$ and $170^{\circ}C$. And the each temperature applied to 300, 600 and 900 hours. The thickness of the intermetallics was measured for each condition and the activation energy for their growth was computed. The fracture surfaces were analyzed using SEM (Scanning Electron Microscope) with EDS (Energy Dispersive Spectroscopy). These results for reliability of lead-free interconnections are discussed.