• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.947-954
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• 2009

This paper proposed a new balanced power amplifier using the reflected input of conventional balanced power amplifiers composed of branch line hybrid coupler. In general, the single-ended amplifier in balanced amplifiers does not have the perfect matching, so the reflected input power, in other words the leakage power, is terminated conventionally at the isolation port of hybrid coupler. However in this work, the leakage power is injected into the auxiliary amplifier, and its output power is combined to the output power of balanced amplifier. Therefore output power, efficiency, and 2-tone IMD3 performances of the proposed balanced amplifier are highly improved compared to the conventional balanced amplifier. For the verification of the proposed balanced amplifier, a conventional balanced amplifier and the proposed balanced amplifier are designed, fabricated and measured, and the measured results are compared. The proposed balanced amplifier shows the improvement in the output power(Pout), power added efficiency (PAE), and 2-tone IMD3 by 3dB, 5.2%, and $5{\sim}10dBc$, respectively, from the measurement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1262-1270
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• 2007

In this paper, we propose a new distortion cancellation mechanism for a balanced power amplifier structure using the carrier cancellation loop of a feedforward and post-distortion technique. The proposed cross post-distortion balanced linear amplifier can reduce nonlinear components as much as the conventional feedforward amplifier through the output dynamic range and broad bandwidth. Also the proposed system provides higher efficiency than the feedforward. The capacities of power amplifier and error power amplifier in the proposed system are analyzed and compared with those of feedforward amplifier. Also the operation mechanisms of the three kind loops are explained. The proposed cross post-distortion balanced linear power amplifier is implemented at the IMT-2000($f_0=2.14\;GHz$) band. With the commercial high power amplifiers of total power of 240 W peak envelope power fer base-station application, the adjacent channel leakage ratio measurement with wideband code division multiple access 4FA signal shows 18.6 dB improvement at an average output power of 40 dBm. The efficiency of fabricated amplifier Improves about 2 % than the conventional feedforward amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.8
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• pp.851-856
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• 2010

This paper presents an efficiency enhancement for the balanced power amplifier using DBS(Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. In order to apply the dynamic biases to each side of the balanced power amplifier, two switching stages are adopted. Using an OFDM signal with a bandwidth of 20 MHz and a PAR(Peak to Average Ratio) of 8.5 dB, 6 % of PAE(Power-Added Efficiency) is improved at an output power of 42.5 dBm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.3
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• pp.437-441
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• 2012

In this paper, we have designed and manufactured 10MHz power source for the application of short distance wireless power transmission. The designed power source consists of a DDS(direct digital synthesizer) signal generator, a buffer driver and a balanced power amplifier. Short range wireless power transmission is usually carried out by near-field inductive coupling between source and load. The distance variation between source and load gives rise to the change of load impedance of power amplifier, which has effect on the operation of power amplifier. To overcome this problem due to load variation of power amplifier, we have adopted the balanced power amplifier using the quadrature hybrid implemented by lumped capacitors and a mutually coupled coil. The experiment results show the above 40dBm output power, frequency range of 9 to 11MHz, and total DC power consumption of 36W.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.606-612
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• 2012

A highly efficient multi-mode balanced power amplifier(PA) structure is proposed for W-CDMA handset applications. The proposed PA has 2-stage amplifier configuration and the stage-bypass and load impedance switching techniques were applied to enhance power efficiency at medium power level as well as low output power level. Using the two techniques, four highly efficient power modes were realized. To demonstrate the usefulness of the proposed structure, a GaAs HBT balanced PA module was designed, fabricated, and measured.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.73-74
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• 2007

In this paper, we design hybrid limitter balanced(HLB) power amplifier with W-CDMA signal input. Balanced power amplifier is important component that decide efficiency in communication system. General balanced power amplifier has low efficiency and high distortion characteristics. Therefore, we embodied two path with limitter that amplitude path had high efficiency amplifier using limitter and phase path had high linear amplifier to improve such problem.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.191-194
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• 1999

The balanced amplifier is a practical amplifier to, implement a broadband amplifier that has flat gain and good input and output VSWR. Three-stage amplifier design procedure usually divided into three partition satisfying the following requirements : low noise figure, high gain and high power output. FHX35LG HEMT device is used in the design can be obtained low noise figure at the first-stage, MGA82563 MMIC device is used in the design can be maintained high gain at the second-stage, and AHI MMIC device is used in the design can be required high power output at the third-stage. The results of three-stage balanced amplifier show that power gain is about 40㏈, noise figure is less than 1.2㏈ at operating frequency.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.326-329
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• 2003

In this paper, we designed and implemented a high power amplifier(HPA) to achieve the high Power Added Efficiency(PAE) over 40% at the 90W output power for the ISM-band(fo=2.45GHz). HPA presented in this paper has 3-stage drive amplifier and 1-stage final amplifier. In the final amplifier, we utilized balanced amplifier configuration with GaAs FET and each of two amplifiers has the push-pull configuration to increase PAE. From the measurement results, we obtained PAE of 42.95% at the 90.57W output power.

• ETRI Journal
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• v.31 no.5
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• pp.598-600
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• 2009

A highly efficient and compactly integrated balanced power amplifier (PA) for W-CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped-element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load-insensitivity under condition of VSWR=4:1.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.68-75
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• 2012

The load-insensitivity of the balanced power amplifier(PA) for W-CDMA handset applications is analyzed. The load impedances of the two parallel amplifiers in the balanced PA depending on the output load mismatch are mathematically calculated and with the result, the phase of reflection coefficient at which the linear output power is severely degraded is investigated. From the analysis, we proposed that the linearity of the balanced PA at the phase can be improved by properly increasing the transistor size and thus, multiple balanced PA's with different transistor size are designed and simulated. The simulation result showed that the balanced PA with larger transistor size has improved linear output power under VSWR=4:1.