• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.4
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• pp.195-200
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• 2009

As 4G mobile communication systems require high transmission rates with reliability, the need for efficient error correcting code is increasing. In this paper, a novel LDPC (Low Density Parity Check) decoder is introduced. The LDPC code is one of the most popular error correcting codes. In order to improve performance of the LDPC decoder, we use SNR (Signal-to-Noise Ratio) estimation results to adjust coefficients of modified UMP-BP (Uniformly Most Probable Belief Propagation) algorithm which is one of widely-used LDPC decoding algorithms. An advantage of Modified UMP-BP is that it is amenable to implement in hardware. We generate the optimal values by simulation for various SNRs and coefficients, and the values are stored in a look-up table. The proposed decoder decides coefficients of the modified UMP-BP based on SNR information. The simulation results show that the BER (Bit Error Rate) performance of the proposed LDPC decoder is better than an LDPC decoder using a conventional modified UMP-BP.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.462-468
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• 2017

In this paper IoT/WSN(Internet of Things/Wireless Sensor Network) has been modeled with a random geometric graph. And a performance of the decentralized code for the efficient storage of data which is generated from WSN has been analyzed. WSN with n=100 or 200 has been modeled as a random geometric graph and has been simulated for their performance analysis. When the number of the total nodes of WSN is n=100 or 200, the successful decoding probability as decoding ratio ${\eta}$ depends more on the number of source nodes k rather than the number of nodes n. Especially, from the simulation results we can see that the successful decoding rate depends greatly on k value than n value and the successful decoding rate was above 70% when $${\eta}{\leq_-}2.0$$. We showed that the number of operations of BP(belief propagation) decoding scheme increased exponentially with k value from the simulation of the number of operations as a ${\eta}$. This is probably because the length of the LT code becomes longer as the number of source nodes increases and thus the decoding computation amount increases greatly.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.57-62
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• 2011

In this paper an efficient LT decoding scheme using GE triangularization is proposed. The proposed algorithm has the desirable performance in terms of both overhead and computational complexity. Belief propagation algorithm is a fast and simple decoding scheme for LT codes. However, for a small code block length k, it requires a large overhead to decode, and OFG which has a small overhead has a large computational complexity. Simulation results show that the proposed algorithm noticeably reduces the computational complexity by more than 1/5 with respect to that of OFG and also its overhead has a small value about 1~5%.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.288-290
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• 2010

PAM이나 QAM과 같은 변조 방식을 이용한 비이진 채널은 BPSK 변조 방식을 사용한 이진 채널과는 다르게 심볼 정보를 이진 확률 정보로 marginalization 하는 과정에서 비이진 심볼을 구성하는 비트 정보 사이의 상관관계 정보가 손실되어 성능 저하를 야기한다. 본 논문은 차세대 3D-HDTV 시스템이 요구하는 높은 전송 효율을 확보하기 위해 사용되는 비이진 채널에 적합한 LDPC 부호화 및 복호화 알고리즘을 소개한다. 또한 GF(q)에서 정의된 비이진 BP 알고리즘이 이진 BP 알고리즘에 비해 보이는 배의 복호 복잡도를 개선하기 위한 대안으로 Coded Marginalization 기법을 제안하고 시뮬레이션을 통해 그 성능을 분석한다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.285-287
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• 2010

본 논문에서는 기존 오류정정부호의 복호 과정에 사용되는 Belief propagation (BP) 알고리즘을 이용한 저밀도 양자 오류정정 부호의 복호 기법에 대해 기술한다. Depolarizing 채널 가정하에 기존 오류정정부호와 다르게 양자 오류정정 부호가 갖는 초기 채널 오류 확률에 의한 성능 열화를 개선하기 위해 초기 채널 오류 확률 정보를 개선하는 기법을 적용하였다. 테너 그래프를 바탕으로 각 체크 노드의 신드롬과 노드의 연결 상태를 고려하여 오류가 발생한 위치를 추적하고 BP 알고리즘에 입력되는 초기 채널 오류 확률 정보를 수정하여 반복 복호 시 발생할 수 있는 성능 열화를 개선하였다.

• Genomics & Informatics
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• v.16 no.4
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• pp.30.1-30.6
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• 2018

There is urgent need for effective and cost-efficient data storage, as the worldwide requirement for data storage is rapidly growing. DNA has introduced a new tool for storing digital information. Recent studies have successfully stored digital information, such as text and gif animation. Previous studies tackled technical hurdles due to errors from DNA synthesis and sequencing. Studies also have focused on a strategy that makes use of 100-150-bp read sizes in both synthesis and sequencing. In this paper, we a suggest novel data encoding/decoding scheme that makes use of long-read DNA (~1,000 bp). This enables accurate recovery of stored digital information with a smaller number of reads than the previous approach. Also, this approach reduces sequencing time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.4
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• pp.79-89
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• 2010

Recently, distributed video coding (DVC) has been actively studied for low complexity video encoder. The complexity of the encoder in DVC is much simpler than that of traditional video coding schemes such as H.264/AVC, but the complexity of the decoder in DVC increases. In this paper, we propose the Region-Of-Interest (ROI) based DVC with low decoding complexity. The proposed scheme uses the ROI, the region the motion of objects is quickly moving as the input of the Wyner-Ziv (WZ) encoder instead of the whole WZ frame. In this case, the complexity of encoder and decoder is reduced, and the bite rate decreases. Experimental results show that the proposed scheme obtain 0.95 dB as the maximum PSNR gain in Hall Monitor sequence and 1.87 dB in Salesman sequence. Moreover, the complexity of encoder and decoder in the proposed scheme is significantly reduced by 73.7% and 63.3% over the traditional DVC scheme, respectively. In addition, we employ the layered belief propagation (LBP) algorithm whose decoding convergence speed is 1.73 times faster than belief propagation algorithm as the Low-Density Parity-Check (LDPC) decoder for low decoding complexity.

• ETRI Journal
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• v.30 no.6
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• pp.807-817
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• 2008

We present a low-density parity-check (LDPC)-based, threaded layered space-time-frequency system with emphasis on the iterative receiver design. First, the unbiased minimum mean-squared-error iterative-tree-search (U-MMSE-ITS) detector, which is known to be one of the most efficient multi-input multi-output (MIMO) detectors available, is improved by augmentation of the partial-length paths and by the addition of one-bit complement sequences. Compared with the U-MMSE-ITS detector, the improved detector provides better detection performance with lower complexity. Furthermore, the improved detector is robust to arbitrary MIMO channels and to any antenna configurations. Second, based on the structure of the iterative receiver, we present a low-complexity belief-propagation (BP) decoding algorithm for LDPC-codes. This BP decoder not only has low computing complexity but also converges very fast (5 iterations is sufficient). With the efficient receiver employing the improved detector and the low-complexity BP decoder, the proposed system is a promising solution to high-data-rate transmission over selective-fading channels.