• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1633-1638
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• 1998

In this paper we propose a generic BIST builder for the Embedded Multiple HAM modules in ASICs, The BlST circuitry is automatically generated according to the specification of the target RAM Modules and the applying test algorithms to them. The lJIST is designed using the TOP-DOWN technique and, thus, has the several advantages in the area of the selection of test algorithm, the development of the circuitry, and the reuse of the circuitry, In addition, we have modified the existing serial interiacing approach to obtain smaller additional BlST circuitry and higher fault coverage and better B1ST sharing of the target RAM Modules in ASICs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.526-531
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• 2003

Recently, many BIST(Built-in Self Test) schemes have been researched to reduce test time and hardware. But, most BIST schemes about pattern generation are for deterministic pattern generation. In this paper a new pseudo-random BIST scheme is provided to reduce the existing test hardware and keep a reasonable length of test time. Theoretical study demonstrates the possibility of the reduction of the hardware for pseudo-random test with some explanations and examples. Also the experimental results show that in the proposed test scheme the hardware for the pseudo-random test is much less than in the previous scheme and provide comparison of test time between the proposed scheme and the current one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2123-2135
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• 1997

In this paepr, we consider resistive shorts on drain-source, drain-gate, and gate-source as well as opens in MOSFETs included in typical memory cell of VLSI SRAM. Behavior of memeory is observed by analyzing voltage at storage nodes of memeory and IDDQ(quiescent power supply current) through PSPICE simulation. Using this behavioral analysis, an effective testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ testing simultaeously is proposed. Built-In Self Test(BIST) circuit which detects faults in memories and Built-In Current Sensor(BICS) which monitors the power supply bus for abnormalities in quescent current are developed and imprlemented to improve the quality and efficiency of testing. Implemented BIST and BICS circuits can detect locations of faults and defects in order to repair faulty memories.

• The Journal of Information Technology
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• v.3 no.3
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• pp.57-65
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• 2000

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell of a 16M SDRAM installed in an Merged Memory with Logic(MML) generating the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by $0.25\mu\textrm{m}$ cell library. and verify the result of Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14N algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.30-36
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• 2012

A new BIST(Built-In Self-Test) scheme to test ADC(Analog-to-Digital Converter) with a transition detector is proposed. The proposed BIST is able to replaces histogram method, the most popular approach in static testing of ADC. With a ramp signal as an input test stimulus, the proposed BIST calculates ADC's static parameters such as offset, gain, INL(Integral Non-Linearity) and DNL(Differential Non-Linearity). The three detectors in the proposed BIST can deal with a transient zone problem, a phenomenon due to random noise in real test environments and are cost efficient at various acceptable ranges determined as a test spec. The simulation results validate that our method performs accurate static test and show the reduction of the hardware overhead.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.635-638
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• 2002

BIST(Built-In Self-Test)를 이용한 테스트 방식은 정상 동작 모드인 회로에 비해 테스트 모드에서 보다 많은 스위칭이 발생하고, 과도한 전력 소모에 의해 회로가 손상을 받을 수 있는 문제점을 갖고 있다. 본 논문은 test-per-clock BIST 구조에서 전력이 제한되어 있을 때 테스트 적용 시간과 총 에너지 소비를 최소화하기 위한 테스트 스케줄링 알고리즘을 제안한다. 제안된 방법은 테스트 세션을 구성함에 있어 각 세션에 포함되는 각 블록의 테스트 시작 시간을 동적으로 결정하여 기존의 알고리즘에 비하여 전력 소모와 전체 테스트 시간을 줄일 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.30-37
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• 2006

This paper presents a modified scan cell architecture to reduce the power dissipation during testing. It not only eliminates switching activities in the combinational logic during scan shifting but also reduces switching activities in the scan chain during the time. Furthermore, it limits the transitions on capture cycles. It can be made for test-per-scan BIST and employed in both single scan style and multiple scan style. Experimental results demonstrate that the proposed structure achieves the same fault coverage with lower power consumption compared to other existing BIST schemes.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.284-292
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• 2008

The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).