• Journal of Digital Contents Society
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• v.17 no.6
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• pp.461-469
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• 2016

A novel steganography based on ternary BCH code with t = 2 is presented in this paper. Proposed method utilizes powerful BCH code with t = 2 for data hiding to the DCT coefficients from JPEG images. The presented data hiding technique uses a proposed look up table approach for searching multiple solutions for ternary BCH code with t = 2. The proposed look up table approach enables fast and efficient search for locations of DCT coefficients, which are necessary to modify for hiding data. Presented data hiding technique is the first steganography technique based on ternary BCH code. Experimental results clearly indicate advantages of using ternary BCH compared to binary BCH.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.6
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• pp.1-7
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• 2010

This paper presents a novel implementation on multimedia fingerprinting algorithm based on BCH (Bose-Chaudhuri-Hocquenghem) code. The evaluation is put in force the colluder detection to n-1. In the proposed algorit hm, the used collusion attacks adopt logical combinations (AND, OR and XOR) and average computing (Averaging). The fingerprinting code is generated as below step: 1. BIBD {7,4,1} code is generated with incidence matrix. 2. A new encoding method namely combines BIBD code with BCH code, these 2 kind codes are to be fingerprinting code by BCH encoding process. 3. The generated code in step 2, which would be fingerprinting code, that characteristic is similar BCH {15,7} code. 4. With the fingerprinting code in step 3, the collusion codebook is constructed for the colluder detection. Through an experiment, it confirmed that the ratio of colluder detection is 86.6% for AND collusion, 32.8% for OR collusion, 0% for XOR collusion and 66.4% for Averaging collusion respectively. And also, XOR collusion could not detect entirely colluder and on the other hand, AND and Averaging collusion could detect n-1 colluders and OR collusion could detect k colluders.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.20-28
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• 2014

This paper proposes a faulty node detection scheme that performs collective monitoring of a distributed networked control systems using interval weighting factor. The algorithm is designed to observe every node's behavior collectively based on the pseudo-random Bose-Chaudhuri-Hocquenghem (BCH) code. Each node sends a single BCH bit simultaneously as a replacement for the cyclic redundancy check (CRC) code. The fault judgement is performed by performing sequential check of observed detected error to guarantee detection accuracy. This scheme can be used for detecting and preventing serious damage caused by node failure. Simulation results show that the fault judgement based on decision pattern gives comprehensive summary of suspected faulty node.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.2
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• pp.1-5
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• 2002

In this paper, a concatenated turbo and BCH coding is proposed for the wireless ATM cell transmission and the bit error rate(BER) and the cell loss ratio(CLR) for the Nosed system is obtained. Turbo code with code rate of 1/2 and BCH code with error correction capability of 5 and 15 bits are used in the simulations. It is shown that the proposed system obtained about 0.2 and 0.4 ㏈ gain over the conventional Turbo code at bit error rate of 0.001. Also the proposed system obtained about 0.1 and 0.2 ㏈ gain over the conventional Turbo code at cell loss rate of 0.01.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.1-9
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• 1993

In this paper, a new digital mobile channel has been modeled. And concatenated code systems have been proposed to transmit information reliably in the newly modeled mobile fading channels. The BCH code has been used as the outer code and the convolutional code as the inner code. We have modeled the channels which have multipath fading phenomena and additive white Gaussian noise. As a result, the characteristics of the channels are identical to that of the mobile fading channel. To find the best code system, we have tested (7, 4), (63, 45), (63, 57) and (31.26) BCH codes as an outer code. Results show that the concatenated code with (7, 4) outer code gives the best performance. And if we use the soft decision, we can improve about 2 -6 dB in the SNR

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.438-449
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• 2012

This paper presents new CRC-p codes for VHF band maritime wireless communication system based on performance analysis of various CRC codes. For this purpose, we firstly describe the method of determination of undetected error probability and minimum Hamming distance according to variation of CRC codeword length. By using the fact that the dual code of cyclic Hamming code and primitive BCH code become maximum length codes, we present an algorithm for computation of undetected error probability and minimum Hamming distance where the concept of simple hardware that is consisted of linear feedback shift register is utilized to compute the weight distribution of CRC codes. We also present construction of transmit data frame of VHF band maritime wireless communication system and specification of major communication parameters. Finally, new optimal CRC-p codes are presented based on the simulation results of undetected error probability and minimum Hamming distance using the various generator polynomials of CRC codes, and their performances are evaluated with simulation results of bit error rate based on the Rician maritime channel model and ${\pi}$/4-DQPSK modulator.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.244-249
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• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.