• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.50-56
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• 2015

An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.111-121
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• 2014

A bi-directional DC-DC converter has been developed for a wireless power transceiver which enables a device to receive and transmit power wireless. Generally, the wireless power transceiver requires two DC-DC covnerter and two external inductors. However, the proposed wireless power transceiver requires only one DC-DC converter and one inductor, allowing small form-factor. The bi-directional DC-DC converter implemented in $0.35{\mu}m$ BCDMOS process operates as a buck converter at the wireless power receiving mode and the power efficiency is 91% when the ouput power is 3W. In the wireless power transmitter mode, the DC-DC converter operates as a boost converter. With the bi-directional DC-DC converter and the proposed efficiency maximizing techniques, the power efficiency of wireless power transceiver is 81.7% in receiver mode and 76.5% in transmitter mode.

• Journal of IKEEE
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• v.23 no.3
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• pp.1104-1107
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• 2019

This paper proposes a DC-DC boost converter for wearable AMOLED display using dead time controller to reduce dead time and improve power efficiency. Also the DC-DC boost converter adopts PWM-SPWM (set-time variable pulse width modulation) dual-mode to enhance power efficiency under light load and decrease output voltage ripple. The proposed circuit has been designed using $0.18{\mu}m$ BCDMOS process. Simulation results show that the circuit has power efficiency of 39%~96% and output ripple voltage of 2 mV under load current range of 1 mA~70 mA. The power efficiency of the proposed circuit is up to 2% higher than the previous PWM-SPWM method and up to 8% higher than only PWM method.

• Journal of IKEEE
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• v.23 no.3
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• pp.1061-1067
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• 2019

In this paper, a highly integrated 3-channel DC-DC converter is designed using power transistor width scaling (PTWS). For positive voltage, $V_{POS}$, a boost converter is designed using the set-time variable pulse width modultaion (SPWM) dual-mode and PTWS to improve efficiency at light load. For negative voltage, $V_{NEG}$, a 0.5 x regulated inverting charge pump is designed with pulse skipping modulation (PSM) controller to reduce power consumption, and for an additional positive voltage, $V_{AVDD}$, a LDO circuit is designed. The proposed DC-DC converter has been designed using a $0.18{\mu}m$ BCDMOS process. Simulation results show that the proposed converter has power efficiency of 56%~90% for load current range of 1 mA~70 mA and output ripple voltage less than 5 mV at positive voltage.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.332-333
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• 2018

This paper presents an advanced abnormal over-current protection with $SuperFET^{(R)}$ 800V MOSFET in Flyback converter. In advanced abnormal over-current protection, digital pattern generator is proposed to detect a steep di/dt current condition when secondary rectifier diode or the transformer is shorted. If current sensing signal is larger than current limit during consecutive switching cycle, Gate signal will be stopped for 7 internal switching periods. If the abnormal over-current maintains pattern, the controller goes into protection mode. The Advanced over-current protection has been implemented in a 0.35um BCDMOS process (ON Semiconductor process).

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.162-163
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• 2007

본 논문에서는 600V/200A 또는 1200V/150A와 같은 고 전력 절연 게이트 소자를 구동 및 보호하기 위한 파워 IC에 대한 연구에 대해서 살펴보았다. 고 전력 소자의 구동을 위해서 최대 Sourcing 전류 4A, 최대 Sinking 전류 8A로 설계하였으며, 과전류 보호회로로는 전력소자의 Desaturation을 검출하는 방식을 사용하였다. 또한 과전류 보호시 발생할 수 있는 과전압을 억제하기 위해서 Soft turn-off 기능을 추가하였다. 동부하이텍의 고전압 BCDMOS 공정인 0.35um BDA350 공정과 PDK를 사용하여 설계 및 제작하였다.

• Journal of Semiconductor Engineering
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• v.3 no.1
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• pp.154-160
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• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.