• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.62-68
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• 1989

In this paper, Analog/Digital BCDMOS technology that the bipolar devices for driver applications CMOS devices for logic applications, and DMOS devices for high voltage applications is pressented. An optimized poly-gate p-well CMOS process is chosen to fabricate the BCDMOS, and the basic concepts to desigh these devices are to improve the characteristics of bipolar, CMOS & DMOS with simple process technology. As the results, $h_{FE}$ value is 320 (Ib-$10{\mu}A$ for bipolar npn transistor, and there is no short channel effects for CMOS devices which have Leff to $1.25{\mu}m$ and $1.35{\mu}m$ for n-channel and p-channel, respectively. Finally, breakdown voltage is obtained higher than 115V for DMOS device.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.82-88
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• 2015

This paper presents a design of the enable switch circuit, which is consist of discrete device at smart junction box(SJB) board. The Enable switch circuit, which receives ignition signal (IG) for input, sends a drive signal to linear regulator and other elements. The circuit design is carried out in a BCDMOS $0.18{\mu}m$ technology, and the performances are verified through simulations according to AEC-Q100 and ISO 7637-2. Die area of the designed Enable switch circuit is $1.67mm{\times}0.54mm$ in layout, and it is shown that the die can be housed in $3mm{\times}3mm$ HVSON8 package. The designed enable switch circuit is expected to be widely adopted in various automotive SJB's since it can significantly reduce the overall printed circuit board form factor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.493-500
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• 2015

A flyback converter operates with either pulse width modulation (PWM) or pulse frequency modulation (PFM) control scheme depending on the load current. At light load condition, PFM control is employed to reduce the switching frequency and thereby minimize the switching power loss. For heavier load, PWM control is used to regulate the output voltage of the flyback converter. The flyback controller has been implemented in a $0.35{\mu}m$ BCDMOS process and applied to a 40-W flyback converter. The light-load power efficiency of the flyback converter is improved up to 5.7-% comparing with the one operating with a fixed switching frequency.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.25-30
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• 2014

This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.96-102
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• 2009

This paper deals with gate drive and power IC for high power devices(600V/200A and 1200V/150A). The proposed gate driver provides high gate driving capability (4 A source, 8 A sink), and over-current protected by means of power transistor desaturation detection. In addition, soft-shutdown function is added to reduce voltage overshoots due to parasitic inductance. This gate drive If is designed, fabricated, and tested using the Dongbu hitek 0.35um BCDMOS process.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.151-161
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• 2013

An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.40-47
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• 2016

In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.61-70
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• 2017

In this paper, an Ethernet equalizer that compensates for automotive temperature variations within a broad range is presented. Communications in automotive systems have become increasingly important because of the many electronics in vehicles. Ethernet protocols are a good candidate for automotive communications. However, they should satisfy the AEC-Q100 requirements that stipulate an operational temperature range from -40 to $150^{\circ}C$. This paper proposes an Ethernet equalizer that can recover data up until 100 m length of CAT-5 cable adaptively within a temperature range of -40 to $150^{\circ}C$. To support the wide temperature range, a feedback system is used. The proposed equalizer has a bandwidth of 31.25 MHz with a fully-differential structure and is implemented in a Hynix $0.13{\mu}m$ BCDMOS technology.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.