• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.329-332
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• 2005

In this paper, we describe implementation of personal media gateway (PMG) for applications over BcN networks. PMG is a TV based set-top terminal, which enables transmission of Full D1 high quality video and audio at the speed of maximum 2Mbps. It supports SIP protocol and QoS for the BcN networks. The hardware of the PMG consists of host module, audio/video codec processing module, DTMF module, and remote control I/O module. H.263 and MPEG4 software are implemented in DSP as codec for hi-directional communication and streaming, respectively. G.711 and Ogg-Vorbis are implemented as audio codec. We examined the quality of video using the Video Quality Test Equpment, which was developed by KT Convergence Lab. The experimental results show the video quality of MOS 4.1 and audio quality of MOS 4.3. We expect that PMG will be prospective business models, and create new customer value.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.181-184
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• 1999

본 논문에서는 MPEG-1 계층 II와 MPEG-2 계층 II LSF 오디오 복호기를 OAK DSP Core를 이용하여 실시간 응용이 가능하도록 구현하였다. Ungrouping시 이용되는 테이블을 효율적으로 사용하였으며 합성필터부의 RAM과 ROM의 크기 그리고 각 부분의 연산에 필요한 연산량을 최적화하기 위하여 알고리듬을 효율적으로 적용하였고 불필요한 연산 부분을 제거하거나 최적화 하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.197-200
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• 1999

MPEG-4 오디오 부호기의 일부인 HVXC(Harmonic and Vector excitation Coding) 부호기는 음성의 무성음 구간에서는 CELP 코덱, 유성음 구간에서는 MBE 코덱을 이용하여 부호화하는 구조로서, 많은 연산량을 필요로 하여 범용DSP를 이용한 실시간 구현의 장애요소로 작용한다. 본 논문에서는 TMS320C6701 DSP를 이용하여 많은 연산 시간을 요하는 함수들에 대한 C언어 및 어셈블리 레벨의 최적화를 수행하여 HVXC 함수들의 실행시간을 단축하고 이를 라이브러리화 하여 실시간 구현에 이용가능 하도록 하였다.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.37-44
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• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6C
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• pp.637-644
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• 2006

This paper presents performance and implementation comparisons of standard and fast DCT algorithms that are commonly used for subband filter bank in MPEG audio coders. The comparison is made according to the architectural difference of the implementation hardware. Fast DCT algorithms are known to have much less computational complexity than the standard method that involves computing a vector dot product of cosine coefficient. But, due to structural irregularity, fast DCT algorithms require extra cycles to generate the addresses for operands and to realign interim data. When algorithms are implemented using DSP processors that provide special operations such as single-cycle MAC (multiply-accumulate), zero-overhead nested loop, the standard algorithm is more advantageous than the fast algorithms. Also, in case of the finite-precision processing, the error performance of the standard method is far superior to that of the fast algorithms. In this paper, truncation errors and algorithmic suitability are analyzed and implementation results are provided to support the analysis.