• Title/Summary/Keyword: Attention Gate

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Electrical Applications of OTFTs

  • Kim, Seong-Hyun;Koo, Jae-Bon;Lim, Sang-Chul;Ku, Chan-Hoi;Lee, Jung-Hun;Zyung, Tae-Hyoung
    • Proceedings of the Polymer Society of Korea Conference
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    • 2006.10a
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    • pp.170-170
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    • 2006
  • [ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.

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A Study on Electrical Characteristics and Optimization of Trench Power MOSFET for Industrial Motor Drive

  • Kang, Ey Goo
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.365-370
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    • 2013
  • Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

An Experimental Study on Injection Molding of Etched Surface Pattern (식각 표면패턴의 사출성형에 관한 실험적 연구)

  • Jing Chung Huang
    • Journal of the Korean Society for Precision Engineering
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    • v.20 no.2
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    • pp.25-32
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    • 2003
  • Molding properties of etched surface pattern are presented. Injection molding has given attention on improving dimensional accuracy and productivity. However, the molding of etched surface pattern on plastic parts is not researched relatively for its additional values, which can meet design function and customer's attraction. Specimens, whose surface patterns are made by print-type etching, are investigated. The molding properties of surface pattern are estimated with roughness deviation of surface pattern on part and mold. The etching properties are related to physical properties of plastic materials and surface roughness of etched pattern. Also, flow mark and gate location can give influence on surface pattern molding. The experimental result can contribute to good molding of surface pattern in injection molding.

Study on Oscillation Circuit Using CUJT and PUT Device for Application of MFSFET′s Neural Network (MFSFET의 신경회로망 응용을 위한 CUJT와 PUT 소자를 이용한 발진 회로에 관한 연구)

  • 강이구;장원준;장석민;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.06a
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    • pp.55-58
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    • 1998
  • Recently, neural networks with self-adaptability like human brain have attracted much attention. It is desirable for the neuron-function to be implemented by exclusive hardware system on account of huge quantity in calculation. We have proposed a novel neuro-device composed of a MFSFET(ferroelectric gate FET) and oscillation circuit with CUJT(complimentary unijuction transistor) and PUT(programmable unijuction transistor). However, it is difficult to preserve ferroelectricity on Si due to existence of interfacial traps and/or interdiffusion of the constitutent elements, although there are a few reports on good MFS devices. In this paper, we have simulated CUJT and PUT devices instead of fabricating them and composed oscillation circuit. Finally, we have resented, as an approach to the MFSFET neuron circuit, adaptive learning function and characterized the elementary operation properties of the pulse oscillation circuit.

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FPGA based POS MPPT Control for a Small Scale Charging System of PV-nickel Metal Hydride Battery (FPGA를 이용한 소형 태양광 발전 니켈 수소 전지 충전 시스템의 POS MPPT 제어)

  • Lee, Hyo-Guen;Seo, Hyo-Ryong;Kim, Gyeong-Hun;Park, Min-Won;Yu, In-Keun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.1
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    • pp.80-84
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    • 2012
  • Recently, the small scale photovoltaic (PV) electronic devices are drawing attention as the upcoming PV generation system. The PV system is commonly used in small scale PV applications such as LED lighting and cell phone. This paper proposes photovoltaic output sensorless (POS) maximum power point tracking (MPPT) control for a small scale charging system of PV-nickel metal hydride battery using field-programmable gate array (FPGA) controller. A converter is connected to a small scale PV cell and battery, and performs the POS MPPT at the battery terminal current instead of being at the PV cell output voltage and current. The FPGA controller and converter operate based on POS MPPT method. The experimental results show that the nickel metal hydride battery is charged by the maximum PV output power.

An Integrated Software Testing Framework for FPGA-Based Controllers in Nuclear Power Plants

  • Kim, Jaeyeob;Kim, Eui-Sub;Yoo, Junbeom;Lee, Young Jun;Choi, Jong-Gyun
    • Nuclear Engineering and Technology
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    • v.48 no.2
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    • pp.470-481
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    • 2016
  • Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

A modified U-net for crack segmentation by Self-Attention-Self-Adaption neuron and random elastic deformation

  • Zhao, Jin;Hu, Fangqiao;Qiao, Weidong;Zhai, Weida;Xu, Yang;Bao, Yuequan;Li, Hui
    • Smart Structures and Systems
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    • v.29 no.1
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    • pp.1-16
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    • 2022
  • Despite recent breakthroughs in deep learning and computer vision fields, the pixel-wise identification of tiny objects in high-resolution images with complex disturbances remains challenging. This study proposes a modified U-net for tiny crack segmentation in real-world steel-box-girder bridges. The modified U-net adopts the common U-net framework and a novel Self-Attention-Self-Adaption (SASA) neuron as the fundamental computing element. The Self-Attention module applies softmax and gate operations to obtain the attention vector. It enables the neuron to focus on the most significant receptive fields when processing large-scale feature maps. The Self-Adaption module consists of a multiplayer perceptron subnet and achieves deeper feature extraction inside a single neuron. For data augmentation, a grid-based crack random elastic deformation (CRED) algorithm is designed to enrich the diversities and irregular shapes of distributed cracks. Grid-based uniform control nodes are first set on both input images and binary labels, random offsets are then employed on these control nodes, and bilinear interpolation is performed for the rest pixels. The proposed SASA neuron and CRED algorithm are simultaneously deployed to train the modified U-net. 200 raw images with a high resolution of 4928 × 3264 are collected, 160 for training and the rest 40 for the test. 512 × 512 patches are generated from the original images by a sliding window with an overlap of 256 as inputs. Results show that the average IoU between the recognized and ground-truth cracks reaches 0.409, which is 29.8% higher than the regular U-net. A five-fold cross-validation study is performed to verify that the proposed method is robust to different training and test images. Ablation experiments further demonstrate the effectiveness of the proposed SASA neuron and CRED algorithm. Promotions of the average IoU individually utilizing the SASA and CRED module add up to the final promotion of the full model, indicating that the SASA and CRED modules contribute to the different stages of model and data in the training process.

Electrical Characteristics of SiO2/4H-SiC Metal-oxide-semiconductor Capacitors with Low-temperature Atomic Layer Deposited SiO2

  • Jo, Yoo Jin;Moon, Jeong Hyun;Seok, Ogyun;Bahng, Wook;Park, Tae Joo;Ha, Min-Woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.265-270
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    • 2017
  • 4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

Estimation of Dynamic Characteristics of Existing Dam Floodgate Using Ambient Vibration (상시 진동을 이용한 댐 수문의 동특성 추정)

  • Kim, Nam-Gyu;Lee, Jong-Jae;Bea, Jung-Ju
    • Journal of the Korean Society for Nondestructive Testing
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    • v.31 no.4
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    • pp.343-350
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    • 2011
  • Recently, as the catastrophic disasters due to earthquake happen frequently all over the world, it draws lots of attention to seismic capacity evaluation and/or structural integrity assessment of deteriorated civil infra-structures. However, there have been few studies on the existing dam flood gates, expecially in Korea. In this study, a proper vibration testing method applicable to a dam flood gate has been suggested, since the dynamic characteristics of a darn flood gate can be fundamental data for seismic capacity evaluation or structural integrity assessment. The frequency domain decomposition technique has been incorporated for modal parameter identification. Two kinds of vibration tests using an impact hammer and ambient vibration sources were carried out on two types of dam floodgates with different shapes. Through the field tests, the effectiveness of the ambient vibration tests were verified.

Reduced Graphene Oxide Field-effect Transistor as a Transducer for Ion Sensing Application

  • Nguyen, T.N.T.;Tien, Nguyen Thanh;Trung, Tran Quang;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.562-562
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    • 2012
  • Recently, graphene and graphene-based materials such as graphene oxide (GO) or reduced graphene oxide (R-GO) draws a great attention for electronic devices due to their structures of one atomic layer of carbon hexagon that have excellent mechanical, electrical, thermal, optical properties and very high specific surface area that can be high potential for chemical functionalization. R-GO is a promising candidate because it can be prepared with low-cost from solution process by chemical oxidation and exfoliation using strong acids and oxidants to produce graphene oxide (GO) and its subsequent reduction. R-GO has been used as semiconductor or conductor materials as well as sensing layer for bio-molecules or ions. In this work, reduced graphene oxide field-effect transistor (R-GO FET) has been fabricated with ITO extended gate structure that has sensing area on ITO extended gate part. R-GO FET device was encapsulated by tetratetracontane (TTC) layer using thermal evaporation. A thermal annealing process was carried out at $140^{\circ}C$ for 4 hours in the same thermal vacuum chamber to remove defects in R-GO film before deposition of TTC at $50^{\circ}C$ with thickness of 200 nm. As a result of this process, R-GO FET device has a very high stability and durability for months to serve as a transducer for sensing applications.

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