• Journal of the Korea Society of Computer and Information
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• v.22 no.11
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• pp.25-30
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• 2017

In this paper, We proposed an effective demosaicking method for single chip RGB-NIR sensors to recover RGB and NIR images. As the method operates in the spatial frequency domain, the frequency domain characteristics of the sampled CFA data are investigated. Using the luminance signal in the frequency domain and the chrominance signals are processed separately with different filters. The simulated images using the real images are compared with other state-of-art methods. As a result, the proposed demosaicking method resulted an effective calculation by a single processing which the existing alternating projection method requires repeated calculation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.74-78
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• 2002

MEMS공정을 이용하여 폴리실리콘의 piezoresistivity를 이용한 스트레인 센서어레이를 제작하였고, 이 센서 어레이를 flexible substrate에 패키징하는 공정을 개발하였다. 실리콘 웨이퍼에 표면 가공(surface micromachining)된 센서는 폴리이미드 코팅, release-etch 방법을 통해 웨이퍼로부터 분리되어 폴리이미드를 기판으로 하는 flexible sensor array module을 완성할 수 있었다. 공정은 희생층과 절연층을 증착하고 폴리실리콘 0.5 $\mu\textrm{m}$을 증착, 도핑 및 패터닝하여 센서 어레이를 구성하였다. 이 센서어레이를 flexible substrate에 패키징 하기 위해서 폴리이미드를 코팅하여 15 $\mu\textrm{m}$의 막을 구성하였고, 100% $O_2$RIE를 이용한 선택적 식각 방법으로 via hole을 구성하였다. 이후 전기도금을 통해 회로를 구성하여 1단계 패키징(die to chip carrier)과 2단계 패키징(chip to substrate)을 웨이퍼 레벨에서 완성하였다. 희생층을 제거함으로서 웨이퍼로부터 센서어레이 모듈을 분리하였다. 제작되어진 센서 모듈은 임의의 곡면에 실장이 가능하도록 충분한 flexibility를 얻을 수 있었다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• Fisheries and Aquatic Sciences
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• v.5 no.1
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• pp.36-42
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• 2002

Microarrayer is used to make DNA chip and microarray that contain hundreds to thousands of immobilized DNA probes on surface of a microscope slide. This paper shows the develop-ment results for a printing type of microarrayer. It realizes a typical, low-cost and efficient microarrayer for generating low density micro array. The microarrayer is developed by using a prependicular type robot with three axes. It is composed of a computer-controlled three-axes robot and a pen tip assembly. The key component of the arrayer is the print-head containing the tips to immobilize cDNA, genomic DNA or similar biological material on glass surface. The robot is designed to automatically collect probes from two 96-well plates with up to 12 pens at the same time. To prove the performance of the developed microarrayer, we use the general water types of inks such as black, blue and red. The inks are distributed at proper positions of 96 well plates and the three color inks are immobilized on the slide glass under the operation procedure. As the result of the test, we can see that it has sufficient performance for the production of low integrated DNA chip consisted of 96 spots within $1cm^2$ area.

• The Journal of Korean Obstetrics and Gynecology
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• v.20 no.4
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• pp.41-55
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• 2007

Purpose: This study is to examine anti-obesity effect and cytotoxicity of the long-term oral administration of Sinomenium acutum (Bang-gi, SA) Methods: Using diet-induced obesity C57BL/6 mouse model, anti-obesity effect and DNA chip expression and cytotoxicity of the long-term oral administration of this herbal extract were investigated. Results: The herbal extract treated groups were arrested in weight increment only when they were lodged together. Such effects were abolished when they kept individually. SA fed mice behaved very rudely and violently. On the basis of histological studies of liver tissues and also in vitro cytotoxicity tests of the liver and kidney cell lines, no significant toxicity was found by 14 weeks of SA treatments. However, we found significant changes in gene expression profile in SA treated group by micro-array analysis. In case of SA group, up-regulated genes were 1,213 and down-regulated ones were 2,558. Some of lipid metabolism related genes also significantly changed in both treatment groups. Conclusion: SA had effects of increasing the basal metabolic rate by stimulating the sympathetic nervous systems.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.225-231
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• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

• Journal of Welding and Joining
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• v.20 no.2
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• pp.90-94
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• 2002

FC-BGA has advantages over other interconnection methods including high I/O counts, better electrical performance, high throughput, and low profile. But, FC-BGA has a lot of reliability issues. The 2nd level solder joint reliability of the FC-BGA with large chip on laminate substrate was studied in this paper. The purpose of this study is to discuss solder joint failures of 2nd level thermal cycling test. This work has been done to understand the influence of the structure of package, the properties of underfill, the properties and thickness of bismaleimide tiazine substrate and the temperature range of thermal cycling on 2nd level solder joint reliability. The increase of bismaleimide tiazine substrate thickness applied to low modulus underfill was improve of solder joint reliability. The resistance of solder ball fatigue was increased solder ball size in the solder joints of FC-BGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1245-1251
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• 1999

A 1.25Gb/s path control switch chip has been designed and implemented with COMPASS tool and 0.8${\mu}{\textrm}{m}$ CMOS gate-array of LG semiconductor. This device controls the path of digital singnals in SDH-based transmission system. The proposed switch chip is suitable for self-healing operations both in a linear network and an unidirectonal ring, The self-healing operation of the switch is effectively done by the configuration information stored in the resisters of the switch. The test device adapted to SDH-based transmission system, show immediate restoration and a 10-11~10-12 bit error raito. And 2.5Gb/s or more high throughput can be realized by combining rwo identical or more switches with the parallel architecture.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.4
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• pp.320-329
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• 2007

Electrokinesis and dielectrophoresis are important transport phenomena produced by external electric field applied to a microchannel containing a conductive fluid. We developed a CFD code to predict electrokinetic and dielectrophoretic flows in a microchannel with a uniform circular post array. Using the code, we calculated particle velocities driven by electrokinesis and dielectrophoresis, and conducted Monte Carlo simulations to visualize the particle motions. The code was validated by comparing the results with those from previous studies in literature. At a low electric field, electrokinesis and diffusion is the dominant transport mechanism. At a moderate electric field, dielectrophoresis is balanced with electrokinesis and diffusion, resulting in flowing filaments of particles in the microchannels. However, dielectrophoresis overwhelms the flow at a high electric field and traps particles locally. These results provide useful insight for optimizing design parameters of a microfluidic chip for biochemical analysis, especially for development of on-chip sample pretreatment techniques using electrokinetic and dielectrophoretic effects.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.