• Journal of Advanced Marine Engineering and Technology
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• v.37 no.4
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• pp.351-357
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• 2013

In flip chip packaging, underfill process is used to fill epoxy bonder into the gap between a chip and a substrate in order to improve the reliability of electronic devices. Underfill process by capillary motion can give rise to unwanted air void formations since the arrangement of solder bumps affects the interfacial dynamics of flow meniscus. In this paper, the unsteady flows in the capillary underfill process are visualized and then the racing effect and merging of the meniscus are investigated according to the arrangement of solder bumps. The result is shown that at higher bump density, the fluid flow perpendicular to the main direction of flow becomes stronger so that more air voids are formed. This phenomenon is more conspicuous at a staggered bump array than at a rectangular bump array.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.563-568
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• 2007

In this paper, the proposed package antenna, which is meander line structure with short pin, is miniaturized to realize RF-SoP at 900 MHz RFID band. The RFID BGA(Ball Grid Array) chip is put in a cavity of LTCC Layers. The coupling and cross talk, which are happen between BGA chip and proposed package antenna, are reduced by faraday cage, which consists of ground and via fences, is realized to enhance the isolation between BGA chip and antenna. The proposed antenna structure is focused on the package level antenna realization at low frequency band. The novel proposed package antenna size is $13mm{\times}9mm{\times}3.51mm$. The measured resonance frequency is 0.893 GHz. The impedance bandwidth is 9 MHz. The maximum gain of radiation pattern is -2.36 dBi.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.2
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• pp.11-19
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• 2009

Thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Using the real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Experiments are conducted for three types of WB-PBGA package that have full grid pattern and perimeter pattern with/without central connections. Bending deformations of the assemblies and average strains of the solder balls are investigated, with an emphasis on the effect of solder interconnection grid patterns, Thermal strain distributions and the location of the critical solder ball in package assemblies are quite different with the form of solder ball grid pattern. For the WB-PBGA-PC, The largest of effective strain occurred in the inner solder ball of perimeter closest to the chip solder balls. The critical solder ball is located at the edge of the chip for the WB-PBGA-FG, at the most outer solder ball of central connections for the WB-PBGA-P/C, and at the inner solder ball closest to the chip for the WB-PBGA-P.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.55-60
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• 2007

This paper presents a compact double resolution scheme for the optical angle sensor based on 1-dimensional CMOS photodiode pixel array. All the pixels are divided into the even pixel and the odd pixel groups. The winner take all circuit is provided for each group. The proposed interpolation scheme increases the resolution by 2 from the winner addresses and winner values. The interpolation scheme can be implemented without any additional pixels or winner take all circuits and require only a comparator and a XOR gate. The proposed pixel array chip that has 336 photodiode pixels with $5.6{\mu}m$ pitch was fabricated with $0.35{\mu}m$ CMOS process and was assembled with a $50{\mu}m$ slit to form an angle sensor. The measured resolution is $0.1{\circ}$ with the proposed interpolation. The chip consumes 35mW and provides 8k samples per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.7-13
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• 2002

BSCT 320${\times}$240 IRFPA detector module is implemented, which is a key component in uncooled thermal imaging systems. The detector module consists of two parts, infrared sensitive pixel array and read-out integrated circuit(ROIC). The BSCT 320${\times}$240 pixels are made by laser scribe process and 10-${\mu}m$ micro-bump to satisfy 50-${\mu}m$ pitch and 95-% fill-factor. The ROIC has been designed to electrically address the pixels sequentailly and to improve signal-to-noise ratio with single transistor amplifier, HPF, tunable LPF and clamp circuit. The fabricated hybrid chip of detector and ROIC has been mounted on the TEC built-in ceramic package for more stable operation and tested for lots of electrical and optical properties. The IRFA sample has shown successful properties and met with good results of fill-factor, detectivity and responsivity.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.3 s.234
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• pp.418-424
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• 2005

We present the design, fabrication and experimental results of 4-bit digital microinjectors, whose ejected droplet volumes are adjusted by the digital operation of a 4-bit microheater array. We design the reference microinjectors as well as its comparative test structures. In the fabrication process, we use a five-mask micromachining process and the total chip size of the fabricated microinjector is $7,640{\mu}m{\times}5,260{\mu}m.$ We measure the ejected droplet volumes and velocities, which are adjusted from $12.1{\pm}1.0~55.6{\pm}14.7pl\;and\;2.3{\pm}0.1~15.7{\pm}0.8m/s.$ respectively, depending on the 15 possible combinations of 4-bit microheater array. We also experimentally characterize the effect of geometric variation including the microheater size, inter-microheater gap, microchannel width and sequential operation of microheater array on the ejected droplet volume and velocity. Among these parameters, we find that the microheater size is the most dominant parameter affected to the ejected droplet volumes and velocities. Thus, the present microinjector has a potential for application to the high-resolution inkjet printers with multiple gray levels or high-precision fluid injectors with variable volume control.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Molecular & Cellular Toxicology
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• v.5 no.3
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• pp.250-256
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• 2009

Toxicogenomics using microarray technology offers the ability to conduct large-scale detections and quantifications of mRNA transcripts, particularly those associated with alterations in mRNA stability or gene regulation. In this study, we developed the HazChem Human Array V2 using the Agilent Sure-Print technology-based custom array, which is expected to facilitate the identification of environmental toxicants. The array was manufactured using 600 VOCs and PAHs-specific genes identified in previous studies. In order to evaluate the viability of the manufactured HazChem human array V2, we analyzed the gene expression profiles of 9 environmental toxicants (6 VOCs chemicals and 3 PAHs chemicals). As a result, nine toxicants were separated into two chemical types-VOCs and PAHs. After the chip validations with VOCs and PAHs, we conducted an expression profiling comparison of additional chemical groups (POPs and EDCs) using data analysis methods such as hierarchical clustering, 1-way ANOVA, SAM, and PCA. We selected 58 genes that could be classified into four chemical types via statistical methods. Additionally, we selected 63 genes that evidenced significant alterations in expression with all 13 environmental toxicants. These results suggest that the HazChem Human Array V2 will expedite the development of a screening system for environmentally hazardous materials at the level of toxicogenomics in the future.