• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.907-910
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• 2003

We have developed Logic Design Training Kit for studying, actual training, designing of FPGA(Xillinx) or CPLD(ALTERA CPLD), the Digital Logic Device. This training kit has 12 matrix keys, RS232 port for serial communication and uses LED array. six FND(Dynamic), LCD as display part. That is standard specification for digital logic training kit. Special point of this kit is that we make two logic device trainig kit. This two logic device kit have more smaller and simple architecture because only uses one chip. That chip already includes a lot of functions that need for training kit, such as : complex logic circuit needed the two kind of logic devices, 16 way of system clock deviding function, serial communication interrupt....etc. We called that one chip is Center Bridge Chipset ; Xillinx FPGA Spartan2. User can select between using one device of FPGA or CPLD, or uses both them. Because of, Center Bridge Chipset has profitable architecture. it can work as Logic Device's networking with Master-Slave connection When using both logic devices.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.847-850
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• 2003

An Eye Ball Sensor (EBS) is a system that locates the point where the user gazes on. The conventional EBS using a CCD camera needs many peripherals, software computation causing high cost and power consumption. This paper proposes a compact EBS using smart CMOS Image Sensor (CIS) pixels. The proposed single chip EBS does not need any peripheral and operates at higher speed and lower cost than the conventional EBS. The test chip was designed and fabricated for 32$\times$32 smart CIS pixel array with a 0.35 um CMOS process occupying 5.3$\textrm{mm}^2$ silicon area.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1571-1574
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• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.

• 전자공학회논문지B
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• 제28B권9호
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.51-53
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• 2002

This research aims to develop a multiple channel electrochemical DNA chip using micro-fabrication technology. At first, we fabricated a high integrated type DNA chip array by lithography technology. Several probe DNAs consisting of thiol group at their 5-end were immobilized on the sold electrodes. Then target DNAs were hybridized by an electrical force. Redox peak of cyclic-voltammogram showed a difference between target DNA and mismatched DNA in the anodic peak current. Therefore, it is able to detect a various genes electrochemically after immobilization of a various probe DNA and hybridization of label-free DNA on the electrodes simultaneously. It suggested that this DNA chip could recognize the sequence specific genes.

• 한국생물공학회소식지
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• 제11권2호
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• pp.35-40
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• 2004

‘바이오칩(biochip)’ 이란 컴퓨터 칩(computer chip)에서 유래되어 바이오(bio)와 관련된 어떤 집적회로의 요소와 관련된 용어로 지칭되어 왔으나, 최근 몇년 동안 기술개발이 구체으로 이루어 지면서, DNA를 포함한 생체분자(biomolecule)에 대하여 생화학적 분석에 사용되는 프로브(probe)를 정렬(array)시킨 물질 및 장치라고 정의되고있다.(중략)

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.89.4-89
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• 2002

$\textbullet$ Field Programmable Gate Array $\textbullet$ flexible hardware $\textbullet$ neural network $\textbullet$ determinism learning $\textbullet$ multi-valued logic $\textbullet$ disjunctive normal form $\textbullet$ multi-dimensional exclusive OR

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 3rd Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.87-119
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• 2001

Fine Pitch Technology will be accelerated among next decade. Buildup Technology is Key Technology for High Density Interconnection. Novel Base Material is critical for High Speed, Area Array Flip Chip Application. Japanese PWB Technology Roadmap will be Published soon.

• 전자공학회지
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• 제31권8호
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• pp.44-51
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• 2004

최근 SoC (System on Chip) 기술의 발전으로 최대 10 Gbps의 처리율을 갖는 네트워크 프로세서가 개발되고 있다. 네트워크 프로세서는 기존의 ASIC (Application Specific Integrated circuit)또는 FPGA (Field Programmable Gate Array) 등 하드웨어가 수행하던 고속의 패킷 처리 기능을 소프트웨어 기반으로 처리하도록 함으로써 다양한 기능의 패킷 처리를 저비용으로 단시간 내에 개발 할 수 있는 장점을 갖고 있다.(중략)

• 전자공학회지
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• 제19권6호
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• pp.55-60
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• 1992

본 논문은 ISDN U-interface 회로 중에서 digital 부분의 설계에 대하여 기술하였다. 이 회로는 MMS43 code와 echo cancellation 방식을 사용하여 구현되었다. 회로 구성상 interface부분과 DSP부분으로 나누어 설계하였으며 gate-array ASIC을 이용하여 chip을 제작하였다. 공정은 1um CMOS 기술을 사용하였다.