• Horticulture, Environment, and Biotechnology : HEB
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• v.59 no.6
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• pp.875-888
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• 2018

Tulip (Tulipa L.) is one of the most important ornamental geophytes in the world. Analysis of molecular variability of tulips is of great importance in conservation and parental lines selection in breeding programs. Of the 70 genic microsatellites, 15 highly polymorphic and reproducible markers were used to assess the genetic diversity, structure, and relationships among 280 individuals of 36 wild and cultivated tulip accessions from two countries: Iran and the Netherlands. The mean values of gene diversity and polymorphism information content were 0.69 and 0.66, respectively, which indicated the high discriminatory power of markers. The calculated genetic diversity parameters were found to be the highest in wild T. systola Stapf (Derak region). Bayesian model-based STRU CTU RE analysis detected five gene pools for 36 germplasms which corresponded with morphological observations and traditional classifications. Based on analysis of molecular variance, to conserve wild genetic resources in some geographical locations, sampling should be performed from distant locations to achieve high diversity. The unweighted pair group method with arithmetic mean dendrogram and principal component analysis plot indicated that among wild tulips, T. systola and T. micheliana Hoog exhibited the closest relationships with cultivated tulips. Thus, it can be assumed that wild tulips from Iran and perhaps other Middle East countries played a role in the origin of T. gesneriana, which is likely a tulip species hybrid of unclear origin. In conclusion, due to the high genetic variability of wild tulips, they can be used in tulip breeding programs as a source of useful alleles related to resistance against stresses.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• Journal of Acupuncture Research
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• v.20 no.4
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• pp.157-169
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• 2003

Objective : The effects of electroacupuncture(EA) stimulation on heart rate variability(HRV) for healthy adults are investigated with power spectrum analysis(PSA) of HRV. Methods : The HRVs of every 10 minute for 22 healthy volunteers(13 men and 9 women) were measured for an hour with SA-3000P(Medicore Co., Ltd., Korea). The median age with arithmetic range of 13 men and 9 women was 26.00 years with 22.75~27.00 years. The initial 20 minutes were defined as baseline period(pre-EA period), the following 20 minutes as the EA period and the last 20 minutes as the post-EA period. In each EA periods, volunteers received EA(2Hz, 0.6~0.8ms duration, maximal tolerated stimulation without discomfort) on the right Zusanli(ST36), Shangjuxu(ST37) acupoints while supine, resting. Results : Heart rate of volunteers at post-EA period was significantly decreased compare to that of pre-EA period, while SDNN at post-EA period was significantly increased. Heart rate at EA period was significantly decreased compare to that of pre-EA period, but Ln(LF) and LF/HF at EA period were significantly increased. Ln(HF) at post-EA period was significantly decreased compare to that of EA period, while the other variables were not significantly changed. Conclusions : The results suggest that EA in healthy adults is associated with changed activity in the sympathetic and parasympathetic nervous system. Further study is needed for investigating the effects of EA on HRV and autonomic nervous system.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.137-147
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• 2013

In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.97-102
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• 2020

This paper relates with the Hybrid-SE-MMA (Signed-Error MMA) that is possible to improving the equalization performance by using the adaptive modulus and adaptive step size in SE-MMA adaptive equalizer for the minimizing the intersymbol interference. The equalizer tap coefficient is updatted use the error signal in MMA algorithm for adaptive equalizer. But the sign of error signal is used for the simplification of arithmetic operation in SE-MMA algorithm in order to updating the coefficient. By this simplification, we get the fast convergence speed and the reduce the algorithm processing speed, but not in the equalization performance. In this paper, it is possible to improve the equalization performance by computer simulation applying the adaptive modulus to the SE-MMA which is proposional to the power of equalizer output signal. In order to compare the improved equalization performance compared to the present SE-MMA, the recovered signal constellation that is the output of the equalizer, residual isi, MD(maximum distortion), MSE and the SER perfomance that means the robustness to the external noise were used. As a result of computer simulation, the Hybrid-SE-MMA improve equalization performance in the residual isi and MD, MSE, SER than the SE-MMA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of Wetlands Research
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• v.7 no.4
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• pp.97-107
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• 2005

As the distributed model is developed and widely used, the accuracy of a rainfall measurement and more dense rainfall observation network are required for the reflection of various spatial properties. However, in reality, it is not easy to get the accurate data from dense network. Generally, we could not have the proper rainfall gages in space and even we have proper network for rainfall gages it is not easy to reflect the variations of rainfall in space and time. Often, we do also have missing rainfall data at the rainfall gage stations due to various reasons. We estimate the distribution of mean areal rainfall data from the point rainfalls. So, in the aspect of continuous rainfall property in time, we should fill the missing rainfall data then we can represent the spatial distribution of rainfall data. This study uses the Fuzzy-Genetic algorithm as a interpolation method for filling the missing rainfall data. We compare the Fuzzy-Genetic algorithm with arithmetic average method, inverse distance method, normal ratio method, and ratio of distance and elevation method which are widely used previously. As the results, the previous methods showed the accuracy of 70 to 80 % but the Fuzzy-Genetic algorithm showed that of 90 %. Especially, from the sensitivity analysis, we suggest the values of power in the equation for filling the missing data according to the distance and elevation.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.160-167
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• 2005

Among finite filed arithmetic operations, division/inverse is known as a basic operation for public-key cryptosystems over $GF(2^{m})$ and it is computed by performing the repetitive $AB^{2}$ multiplication. This paper presents a digit-serial-in-serial-out systolic architecture for performing the $AB^2$ operation in GF$(2^{m})$. To obtain L×L digit-serial-in-serial-out architecture, new $AB^{2}$ algorithm is proposed and partitioning, index transformation and merging the cell of the architecture, which is derived from the algorithm, are proposed. Based on the area-time product, when the digit-size of digit-serial architecture, L, is selected to be less than about m, the proposed digit-serial architecture is efficient than bit-parallel architecture, and L is selected to be less than about $(1/5)log_{2}(m+1)$, the proposed is efficient than bit-serial. In addition, the area-time product complexity of pipelined digit-serial $AB^{2}$ systolic architecture is approximately $10.9\%$ lower than that of nonpipelined one, when it is assumed that m=160 and L=8. Additionally, since the proposed architecture can be utilized for the basic architecture of crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity and pipelinability.