• 한국수학교육학회지시리즈D:수학교육연구
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• 제12권1호
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• pp.49-66
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• 2008

In this paper we present a cognitive developmental analysis of the arithmetic mean concept. This analysis leads us to a hierarchical classification at different levels of understanding of the responses of 227 students to a questionnaire which combines open-ended and multiple-choice questions. The SOLO theoretical framework is used for this analysis and we find five levels of students' responses. These responses confirm different types of difficulties encountered by students regarding their conceptualization of the arithmetic mean. Also we have observed that there are no significant differences between secondary school and university students' responses.

• 한국수학사학회지
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• 제22권4호
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• pp.83-96
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• 2009

이 논문은 광무(光武) 융희연간(隆熙年間)(1897~1910)에 걸쳐 각급 학교에서 사용할 목적으로 편찬 간행된 산술교과서(算術敎科書)의 초기 편찬사를 더듬어 본 것이다. 이 시기의 산술교과서(算術敎科書)는 비록 확고한 편찬 방침 아래 편찬된 것이 아닌 주로 일본에서 간행 되었던 산술교과서(算術敎科書)를 번역 내지 번안한 것이 대부분이지만 오늘날의 수학교과서에 적지 않은 영향을 미치고 있음을 생각할 때, 우리나라의 수학교과서의 역사를 연구함에 있어서 대단히 중요한 사료적 가치(史料的 價値)를 갖고 있다고 할 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.778-780
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• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 1998년도 제28회 추계학술대회
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• pp.292-299
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• 1998

The effect of characteristic of surface roughness on friction and sliding wear was studied experimentally with ball-on-disk type wear tester. The test was conducted with specimens those have varying arithmetic mean value, skewness and kurtosis under the condition of different load, sliding speed and lubricant viscosity. The surface of the lower skewness in negative value or the highel kurtosis tends to have low friction for the same arithmetic mean value. There is optimum arithmetic mean value surface roughness for operating variables have load, speed, etc.

• 전기전자학회논문지
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• 제18권4호
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Kyungpook Mathematical Journal
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• 제54권4호
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• pp.521-529
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• 2014

In this paper we derive some optimal convex combination bounds related to arithmetic mean. We find the greatest values ${\alpha}_1$ and ${\alpha}_2$ and the least values ${\beta}_1$ and ${\beta}_2$ such that the double inequalities $${\alpha}_1T(a,b)+(1-{\alpha}_1)H(a,b)<A(a,b)<{\beta}_1T(a,b)+(1-{\beta}_1)H(a,b)$$ and $${\alpha}_2T(a,b)+(1-{\alpha}_2)G(a,b)<A(a,b)<{\beta}_2T(a,b)+(1-{\beta}_2)G(a,b)$$ holds for all a,b > 0 with $a{\neq}b$. Here T(a,b), H(a,b), A(a,b) and G(a,b) denote the second Seiffert, harmonic, arithmetic and geometric means of two positive numbers a and b, respectively.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• East Asian mathematical journal
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• 제27권2호
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• pp.243-259
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• 2011

The Yang-Hui arithmetic(楊輝算法) is a crucial textbook on mathematics for make out the Orient mathematics. In this thesis, compare the Yang-Hui arithmetic and the part of the equation and the function both in the middle school mathematics of the 7th Educational Curriculum Revision. As well, drawing a parallel between two things is the solution that had given in the Yang-Hui arithmetic and have given in the middle school textbook of the 7th Educational Curriculum Revision.

• 콘크리트학회논문집
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• 제17권6호
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• pp.1045-1051
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• 2005

For critical structures and application, where a given reliability must be met, it is necessary to account for uncertainties and variability in material properties, structural parameters affecting the corrosion process, in addition to the statistical and decision uncertainties. This paper presents an approach to the fuzzy arithmetic based modeling of the chloride-induced corrosion of reinforcement in concrete structures that takes into account the uncertainties in the physical models of chloride penetration into concrete and corrosion of steel reinforcement, as well as the uncertainties in the governing parameters, including concrete diffusivity, concrete cover depth, surface chloride concentration and critical chloride level for corrosion initiation. The parameters of the models are regarded as fuzzy numbers with proper membership function adapted to statistical data of the governing parameters and the fuzziness of the corrosion time is determined by the fuzzy arithmetic of interval arithmetic and extension principle

• 전기전자학회논문지
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• 제14권2호
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• pp.64-68
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• 2010

본 논문은 작은 사이즈가 요구되는 제한적인 모바일 환경의 프로세서에서 별도의 연산기 없이 제안된 Dual Phase 명령어 구조를 이용해 효율적인 로그와 지수 연산이 가능한 방법을 제안한다. Floating Point 자료형의 지수부와 실수부를 추출하는 명령어 세트와 테일러 급수 전개를 이용해 로그의 근사치를 계산하여 24비트 단정도 부동 소수점을 연산하고, Dual Phase 명령어 구조를 활용해 명령어 실행 사이클을 줄였다. 제안된 구조는 별도의 연산기를 두는 구조보다 작은 사이즈를 유지하면서 성능저하를 33%까지 최소화 할 수 있는 구조이다.