• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.913-921
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• 2007

Retargetable compiler which generates executable code for a target processor and performance profiler are required to design a processor optimized for a specific application. This paper presents an architecture exploration methodology based on ADL (Architecture Description Language). We synthesized instruction set and optimized processor structure using information extracted from application program. The information of operation sequences executed frequently and register usage are used for processor optimization. Architecture exploration has been performed for JPEG encoder to show the effectiveness of the system. The ASIP designed using the proposed method shows 1.97 times better performance.

• Asia pacific journal of information systems
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• v.28 no.4
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• pp.240-257
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• 2018

In today's turbulent business landscape, a firm's ability to explore new IT capabilities and exploit current ones is essential for enabling organizational agility and achieving high organizational performance. We propose IT exploration and exploitation as two critical organizational learning processes that are essential for gaining and sustaining competitive advantages. However, it remains unclear how the emerging cloud-based IT architecture affects an organization's ability to explore and exploit its IT capabilities. We conceptualize modularity and virtuality as two critical dimensions of emerging cloud-based IT architecture and investigate how they affect IT exploration and exploitation. We test our hypotheses using data obtained from our field survey of IT managers. We find that modularity is positively associated with both exploration and exploitation whereas virtuality is positively associated with exploration, but not with exploitation. We also find that the effect of modularity on exploitation is stronger than its effect on exploration.

• Journal of Astronomy and Space Sciences
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• v.41 no.1
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• pp.43-60
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• 2024

Korea Pathfinder Lunar Orbiter (KPLO) is South Korea's first space exploration mission, developed by the Korea Aerospace Research Institute. It aims to develop technologies for lunar exploration, explore lunar science, and test new technologies. KPLO was launched on August 5, 2022, by a Falcon-9 launch vehicle from cape canaveral space force station (CCSFS) in the United States and placed on a ballistic lunar transfer (BLT) trajectory. A total of four trajectory correction maneuvers were performed during the approximately 4.5-month trans-lunar cruise phase to reach the Moon. Starting with the first lunar orbit insertion (LOI) maneuver on December 16, the spacecraft performed a total of three maneuvers before arriving at the lunar mission orbit, at an altitude of 100 kilometers, on December 27, 2022. After entering lunar orbit, the commissioning phase validated the operation of the mission mode, in which the payload is oriented toward the center of the Moon. After completing about one month of commissioning, normal mission operations began, and each payload successfully performed its planned mission. All of the spacecraft operations that KPLO performs from launch to normal operations were designed through the system operations design process. This includes operations that are automatically initiated post-separation from the launch vehicle, as well as those in lunar transfer orbit and lunar mission orbit. Key operational procedures such as the spacecraft's initial checkout, trajectory correction maneuvers, LOI, and commissioning were developed during the early operation preparation phase. These procedures were executed effectively during both the early and normal operation phases. The successful execution of these operations confirms the robust verification of the system operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• ETRI Journal
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• v.38 no.6
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• Journal of Ocean Engineering and Technology
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• v.22 no.4
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• pp.72-77
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• 2008

General aspects of deepwater petroleum exploration and production were identified and related technical challenges were addressed. Historical perspectives, insight, processes, and engineering applications are reviewed to enhance the design capability of the domestic offshore industry. The technical challenges and unique aspects of deepwater exploration and production were identified. The assessment of deepwater exploration, drilling, and production systems is a key stage for performing the front end engineering design (FEED). The global trends in deepwater development, including the feasibility for Korea, were reviewed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.78-85
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• 2008

This paper presents a high-level design methodology applied on an SoC using SystemC. The topic will emphasize on high-level design approach for intensive architecture exploration and verifying cycle accurate SystemC models comparative to real Verilog RTL models. Unlike many high-level designs, we started the poject with working Verilog RTL models in hands, which we later compared our SystemC models to real Verilog RTL models. Moreover, we were able to use the on-chip test board performance simulation data to verify our SystemC-based platform. This paper illustrates that in high-level design, we could have the same accuracy as RTL models but achieve over one hundred times faster simulation speed than that of RTL's. The main topic of the paper will be on architecture exploration in search of performance degradation in source.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12B
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• pp.1758-1765
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• 2010

This paper proposes an architecture exploration methodology for the design of embedded cores exploiting design hierarchy. The proposed method performs systematic architecture exploration by taking different approaches for verifying designs and estimating performances depending on the hierarchy level in design process. Performance estimation tools generate profile having performance data related with design modules of an embedded core. Profile analyzer performs data-mining to acquire association rules between the design modules and performance parameters. Inference engine in the profile analyzer updates the association rules which will be used to improve the design performance at next exploration steps. To show the efficiency of the proposed architecture explorations methodology, experiments had been performed for JPEG encoder, Chen-DCT, and FFT application functions. The embedded cores designed by taking the proposed method show performance improvement by 60.8% in terms of clock cycles on the average when compared with the initial embedded core in MIPS R3000.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.01a
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• pp.1-4
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• 2014

Although physical modeling synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research of single-instruction multiple-data many-core architectures that support the tremendous amount of computations by exploiting massive parallelism inherent in physical modeling synthesis. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, design space exploration is conducted for seven processing element (PE) configurations. To find an optimal PE configuration, each PE configuration is evaluated in terms of execution time, area and energy efficiencies. Experimental results show that all PE configurations are satisfied with the system requirements to be implemented in portable devices.

• Korean Architects
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• s.592
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• pp.140-151
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• 2018