• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2010년도 추계학술대회
• /
• pp.84-87
• /
• 2010

본 논문에서는 power management IC에 사용되는 아날로그 트리밍용 antifuse OTP 셀을 제작하였다. VPP (=7V)와 VNN (=-5V)의 Dual program voltage를 이용하는 antifuse OTP 셀은 antifuse 양단에 hard breakdown 이상의 전압을 인가하여 thin gate oxide를 breakdown시킨다. $0.18{\mu}m$ BCD 공정을 이용하여 제작된 antifuse OTP 셀의 면적은 $48.01{\mu}m^2$으로 eFuse OTP 셀 면적의 44.6% 수준이다. 20개의 테스트 패턴을 측정한 결과 프로그램 후 antifuse의 저항은 수 $k{\Omega}$ 이하로 양호하게 측정되었다.

• 한국전기전자재료학회논문지
• /
• 제14권12호
• /
• pp.953-958
• /
• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• 한국진공학회지
• /
• 제6권3호
• /
• pp.194-199
• /
• 1997

Al/a-Si:H/Mo 구조의 MIM(Metal-Insulator-Metal) antifuse를 제작하여 antifuse의 I-V 특서을 조사하고, 온저항의 분포를 구하였다. 제작된 antifuse의 누설전류는 1pA/$\mu\textrm{m}^2$이하였고, 프로그래밍 전압은 10~11V 내에 분포하였다. 프로그램 후 온저항은 대부분 10~20 Ω이었고, 20%정도는 100$\Omega$이상의 분포도를 보였다. 이러한 온저항 분포의 편차와 저항값을 줄이기 위해 이미 프로그램된 antifuse에 다시 전류를 주입하는 재 프로그래밍 방법을 시도 하였다. 이 방법을 통하여 100$\Omega$이상의 온저항을 가지는 antifulse를 다시 50$\Omega$이하로 낮출 수 있었다. 재 프로그래밍 방법을 사용한 antifuse는 한번만 프로그래밍 했을 때 보다 더욱 더 균일하고 낮은 온저항 분포를 가졌다.

• 한국정보통신학회논문지
• /
• 제13권9호
• /
• pp.1858-1864
• /
• 2009

본 논문에서는 power management IC에 사용되는 비휘발성 메모리 IP인 1-kd OTP IP를 설계하였다. 기존의 OTP 셀 (cell)은 isolated NMOS 트랜지스터를 안티퓨즈 (antifuse)로 사용하였으나 BCD 공정에서는 셀 크기가 큰 단점이 있다. 그래서 본 논문에서는 isolated NMOS 트랜지스터 대신 PMOS 트랜지스터를 안티퓨즈로 사용하였으며, OTP 셀 트랜지스터의 크기를 최적화시켜 셀의 크기를 최소화시켰다. 그리고 ESD 테스터 시 PMOS 안티퓨즈 양단에 고전압 (high voltage)가 걸려 임의의 셀이 프로그램 되는 것을 방지하기 위하여 OTP 코어 회로에 ESD 보호 회로 (protection circuit)를 추가하였다. 또한 프로그램 되지 않은 셀을 읽을 때 게이트 커플링 노이즈를 제거하기 위해 high-impedance의 PMOS pull-up 트랜지스터를 ON 시키는 방식을 제안하였다. 동부하이텍 $0.18{\mu}m$ BCD 공정을 이용하여 설계된 1-kb PMOS-type 안티퓨즈 OTP IP의 레이아웃 크기는 $129.93{\times}452.26{\mu}m^2$이다.

• 한국진공학회지
• /
• 제4권1호
• /
• pp.46-50
• /
• 1995

물성을 달리한 $\alpha$-Si을 사용하여 MIM(Metal-Insulator-Metal)구조의 antifuse들을 제작하고, 물성의 변화에 따른 전기적 특성의 변화를 조사하였다. $\alpha$-Si은 PECVD (Plasma Enhanced Chemical Vapor Deposition)방법으로 증착하였으며, 물성은 RF power를 달리하여 변화시켰다. $\alpha$-Si MIM구조의 antifuse를 프로그램할 때 생기는 failure rate를 줄이기 위해 전극 사이에 삽입되는 $\alpha$-Si의 contact hole 크기와 개수를 변화시켜 보았다. MIM antifuse는 contact hole이 2개 이상일 때 failure rate가 10% 이내로 줄었으며, 프로그래밍 전류는 거의 변화가 없었다. 항복전압은 10-11V범위에 집중적으로 분포하였으며, 5V에서의 누설전류는 contact hole의 수가 증가함에 따라 커짐을 알았다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권4호
• /
• pp.216-231
• /
• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• 한국전기전자재료학회논문지
• /
• 제13권4호
• /
• pp.273-279
• /
• 2000

Electrical repair method which has replaced laser repair method can replace defective cell by redundancy’s in the redundancy scheme of conventional high density memory. This electrical repair circuit consists of the antifuse program/read/latch circuits, a clock generator a negative voltage generator a power-up pulse circuit a special address mux and etc. The measured program voltage of made antifuses was 7.2~7.5V and the resistance of programmed antifuses was below 500 Ω. The period of clock generator was about 30 ns. The output voltage of a negative voltage generator was about 4.3 V and the current capacity was maximum 825 $mutextrm{A}$. An antifuse was programmed using by the electric potential difference between supply-voltage (3.3 V) and output voltage generator. The output pulse width of a power-up pulse circuit was 30 ns ~ 1$mutextrm{s}$ with the variation of power-up time. The programmed antifuse resistance required below 44 ㏀ from the simulation of antifuse program/read/latch circuit. Therefore the electrical repair circuit behaved safely and the yield of high densitymemory will be increased by using the circuit.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권4호
• /
• pp.205-210
• /
• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• 전자공학회논문지A
• /
• 제32A권11호
• /
• pp.63-69
• /
• 1995

A novel programming architecture for antifuse FPGA(Field Programmable Gate Array) is described. This architecture prevents programming transistors from breakdown which occurs due to high voltage across the transistors during antifuse programming. Extra mask and processes can be avoided using this proposed architecture. To reduce the applied voltage across the terminals of programming transistors, different voltage ranges are supplied to vertical and horizontal tracks; between programming voltage Vp and Vp/2 for vertical tracks and between Vp/2 and 0V for horizontal tracks. Therefore, Maximum voltage across the programming transistors is half of the programming voltage and an designated antifuse can be programmed by applying maximum voltage for vertical track and minimum voltage for horizontal track while others are subjected to voltage difference below Vp/2.

• 전자공학회논문지D
• /
• 제35D권7호
• /
• pp.72-78
• /
• 1998

This paper is focused on the fabrication of reliable novel antifuse, which could operate at low voltage along with the improvement in OFF and ON-state properties. The fabricated antifuse consists of Al/BaTi$_{2}$O$_{3}$/SiO$_{2}$/TiW-silicide structure. Through the systematic analyses for bottom metal and the intermetallic insulator, material and electri cproperties were investiaged. TiW-silicide as the bottom electrode had smooth surface with average roughness of 11.angs. at 10X10.mu.m$^{2}$ and was bing kept as-deposited SiO$_{2}$ film stable. Amorphous BaTi$_{2}$O$_{3}$ film as the another insulator was chosen because of its low breakdown strength (2.5MV/cm). breakdown voltage of antifuse is remarkably reduced by using BaTi$_{2}$O$_{3}$ film, and leakage current of that maintained low level due to the SiO$_{2}$ film. Low ON-resistance (46.ohm./.mu.m$^{2}$) and low programming voltage(9.1V) can be obtained in theses antifuses with 220.angs. double insulator layer and 19.6X10$^{-6}$ cm$^{2}$ area, while keeping sufficient OFF-state reliability (less than 1nA).