• Journal of Magnetics
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• 제6권4호
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• pp.126-128
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• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.593-596
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• 1998

Effects of current re-stress after anneal on leakage current and trapped charges in oxides are investigated. Current stress on 6 nm thick oxide has generated mostly positive traps within the oxide resulting in leakage currents. The interface states generated are several orders of magnitude smaller, determined by C-V and charge pumping method. Annealing has eliminated only the charged traps not the neutral traps, thus the leakage current and trap density are increased when the oxides are re-stressed.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.63-63
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• 2001

디바이스의 크기가 0.25㎛이하로 축소됨에 따라 DRAM(Dynamic Random Access Memory) 제조업체들은 칩 크기를 줄이고 지역적인 배선으로 사용하기 위해서 기존의 텅스텐-폴리사이드 비트-선에서 텅스텐 비트-선으로 대체하고 있다. 본 논문에서는 다양한 RTP 온도와 추가 이온주입을 사용하여 낮은 저항을 갖는 텅스텐 비트-선 제조 공정에 대해 다루었다. 그 결과 텅스텐 비트선 저항에 중요한 메계변수는 RTP Anneal 온도와 BF₂ 이온 주입 도펀트임을 알 수 있었다. 이러한 텅스텐 비트-선 공정은 고밀도 칩 구현에 중요한 기술이 된다.

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.37-42
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• 2004

본 논문에서는 선비정질화, 저에너지 이온 주입, 이중 열처리 공정을 이용하여 p/sup ＋/-n 박막 접합을 형성하였다. Ge 이온을 이용하여 결정 Si 기판을 선비정질화하였다. 선비정질화된 시편과 결정 기판에 p-형 불순물인 BF₂이온을 주입하여 접합을 형성하였다. 열처리는 급속 열처리 (RTA : rapid thermal anneal) 방법과 850℃의 노 열처리 (FA : furnace anneal) 방법을 병행하였다. 두 단계의 이중 열처리 방법으로 네 가지 조건을 사용하였는데, 이는 RTA(750℃/10초)＋Ft, FA＋RTA(750℃/10초), RTA(1000℃/10초)＋F4 FA＋RTA(1000℃/10초)이다. Ge 선비정질화를 통하여 시편의 접합 깊이를 감소시킬 수 있었다. RTA 온도가 1000℃인 경우에는 RTA보다는 FA를 먼저 수행하는 것이 접합 깊이(x/sub j/), 면저항(R/sub s/), R/sub s/ x/sub j/, 누설 전류 등의 모든 면에서 유리함을 알 수 있었다.

• Journal of Radiation Protection and Research
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• 제22권3호
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• pp.135-141
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• 1997

열처리 특성의 연구는 열형광선량계를 재 사용하는데 있어서 중요하다. 최근 개발된 디스크 형태 (직경 4.5 mm, 두께 약 $90mg/cm^2$)의 LiF:Mg,Cu,Na,Si Teflon TLD의 열처리 조건을 구하기 위하여 조사전열처리, 판독과정 및 판독 후 열처리의 순서로 연구하였다. Teflon TLD의 감마선 조사는 $^{60}Co$ 0.1 Gy로 하였다. LiF:Mg,Cu,Na,Si Teflon TLD의 열처리 특성의 연구는 전기로와 판독장치를 이용하여 열처리 온도와 열처리 시간을 변화시키면서, 측정반복횟수에 따른 열형광강도 변화를 관찰하는 방법으로 수행하였다. LiF:Mg,Cu,Na,Si Teflon TLD의 열처리 조건은 조사전 열처리를 $80^{\circ}C$에서 1 시간 한 후 $280^{\circ}C$까지 판독하고 판독 후 열처리를 $270^{\circ}C$에서 20 초간 하는 것으로 결정되었고, 이 조건에서 10 회 반복측정시 원래의 열형광강도는 5%의 감소를 보였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.364-368
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• 1997

We have investigated Pt and RuO$_2$as a bottom electrode for a device application of PZT thin film. The bottom electrodes were prepared by using an RF magnetron sputtering method. We studied some of the property influencing factors such as substrate temperature, gas flow rate, and RF power. An oxygen partial pressure from 0 to 50% was investigated. The results show that only Ru metal was grown without supp1ying any O$_2$gas. Both Ru and RuO$_2$phases were formed for O$_2$partial pressure between 10∼40%. A Pure RuO$_2$ phase was obtained with O$_2$partial pressure of 50%. A substrate temperature from room temperature to 400$^{\circ}C$ was investigated with XRD for the film crystallinity examination. The substrate temperature influenced the surface morphology and the resistivity of Pt and RuO$_2$as well as the film crystal structure. From the various considerations, we recommend the substrate temperature of 300$^{\circ}C$ for the bottom electrode growth. Because PZT film growth on top of bottom electrode requires a temperature process higher than 500$^{\circ}C$, bottom electrode properties were investigated as a function of post anneal temperature. As post anneal temperature was increased, the resistivity of Pt and RuO$_2$was decreased. However, almost no change was observed in resistivity for an anneal temperature higher than 700$^{\circ}C$. From the studies on resistivity and surface morphology, we recommend a post anneal temperature less than 600$^{\circ}C$.

• 한국재료학회지
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• 제12권10호
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.375-381
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• 2001

디바이스의 크기가 0.25㎛이하로 축소됨에 따라 DRAM(Dynamic Random Access Memory) 제조업체들은 칩 크기를 줄이고 지역적인 배선으로 사용하기 위해서 기존의 텅스텐-폴리사이드 비트-선에서 텅스텐 비트-선으로 대체하고 있다. 본 논문에서는 다양한 RTP 온도와 추가 이온주입을 사용하여 낮은 저항을 갖는 텅스텐 비트-선 제조 공정에 대해 다루었다. 그 결과 텅스텐 비트선 저항에 중요한 메계변수는 RTP Anneal 온도와 BF₂ 이온 주입 도펀트임을 알 수 있었다. 이러한 텅스텐 비트-선 공정은 고밀도 칩 구현에 중요한 기술이 된다.

• Advances in nano research
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• 제2권4호
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• pp.179-186
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• 2014

Indium-nitrogen co-doped zinc oxide thin films (INZO) were prepared on glass substrates in the atmosphere by ultrasonic spray pyrolysis. The aqueous solution of zinc acetate, ammonium acetate and different indium sources: indium (III) chloride and indium (III) nitrate were used as the precursors. After film deposition, different anneal temperature treatment as 350, 450, $550^{\circ}C$ were applied. Electrical properties as concentration and mobility were characterized by Hall measurement. The surface morphology and crystalline quality were characterized by SEM and XRD. With the activation energy analysis for both films, the concentration variation of the films at different heat treatment temperature was realized. Donors correspond to zinc related states dominate the conduction mechanism for these INZO films after $550^{\circ}C$ high temperature heat treatment process.

• 센서학회지
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• 제6권6호
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• pp.483-490
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• 1997

Thin film Si has been used in sensors, radiation detectors, and solar cells. The carrier mobility of thin film Si influences the device behavior through its frequency response or time response. Since poly-Si shows the higher mobility value, a-Si:H films on Mo substrate were subjected to various crystallization treatments. Consequently, we need to find an appropriate method in mobility measurement before and after the anneal treatment. This paper investigates the carrier mobility improvement with anneal treatments and summarizes the mobility measurement methods of the a-Si:H and poly-Si film. Various techniques were investigated for the mobility determination such as Hall mobility, HS, TOF, SCLC, TFT, and TCO method. We learned that TFT and TCO method are suitable for the mobility determination of a-Si:H and poly-Si film. The measured mobility was improved by $2{\sim}3$ orders after high temperature anneal above $700^{\circ}C$ and grain boundary passivation using an RF plasma rehydrogenation.