• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1812-1819
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• 2001

In this paper, it investigated the permitted limit of the analog nonideality for the SOSOC Σ-Δ modulator design which is satisfied with 1 [MHz] signal bandwidth and 12-bit resolution in the OSR=25. Firstly, it get the SOSOC Σ-Δ modulator model and gain coefficient which is suitable in low voltage for the Σ-Δ modulator design which is satisfied with the specification in the supply voltage 3.3 [Vl. And it provided the performance prediction of the Σ-Δ modulator and the permitted limit of the nonideality by adding the performance degradation facts of the Σ-Δ modulator such as the finite gain of the amplifier, the SR, the closed-loop pole, the switch ON resistance and the capacitor mismatch to the ideal Σ-Δ modulator model. When designed the Σ-Δ modulator which is satisfied with the specification by the base above, it will be able to predict the performance of the Σ-Δ modulator and the guide for the specification of the circuit which composes the Σ-Δ modulator.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.453-462
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• 2010

The switch from analog to digital broadcast television is extended rapidly. The DTV can offer multiple programming choices, interactive capabilities and so on. Moreover, with the spread of Internet, the information exchange between the communities is increasing, too. These facts lead to the new TV service environment which can offer customized TV programs to personal/community users. This paper proposes a 'Customized Digital TV System for Individuals/Communities based on Data Stream Mining' which can analyze user's pattern of TV watching behavior. Due to the characteristics of TV program data stream and EPG(electronic program guide), the data stream mining methods are employed in the proposed system. When a user is watching DTV, the proposed system can control the surrounding circumstances as using the user behavior profiles. Furthermore, the channel recommendation system on the smart phone environment is proposed to utilize the profiles widely.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.79-85
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• 2016

Recently, visible light communication(VLC) is being actively researched as green wireless communication services are drawing attention. Currently, VLC mostly uses LED for transmission and PD(Photo Diode) for receiving. However, this kind of system has limited applications. Therefore, we design and propose in this paper, a LED-to-LED two way VLC system that doesn't use PD(Photo Diode). This system has the following features and contributions. First, this system uses just LED at both transmitter and receiver with analog switch, Second, this system support both one-way communication and two way communication together. One way communication can support multi-hop communication. The performance evaluation of the proposed system is conducted at a place with standard light. We test the success or failure of one way communication by changing distance and baud rate while test the success and failure of two way communication by changing distance. We expect that the proposed LED-to-LED system in this paper can be applied for various application fields.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.745-752
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• 2016

In the era of the Internet of Things, where all physical objects are connected to the Internet, we suggest a remote control system using a Raspberry Pi single-board computer with ZigBee, which can turn an indoor light-emitting diode (LED) and a multiple-tap on and off, and with a smart phone can control the brightness of the LED as well as an electronic door lock. By connecting an infrared (IR) transmitter module to the Raspberry Pi, we can control home appliances, such as an air conditioner, and we can also monitor indoor images, indoor temperatures, and illumination by using a smart phone app. We developed a method of finding out IR transmission codes required for remote-controllable appliances with an AVR micro-controller. We suggest a method to remotely open and shut an office door by novating the door lock. The brightness level of an LED (between 0 and 10) can be controlled through a PWM signal generated by an ATmega88 microcontroller. A mutiple-tap is controlled using an ATmega32, a photo-coupler, and a TRIAC. The signals for measured temperature and illumination are converted from analog to digital by using the ATtiny44A microcontroller transmitting to a Raspberry Pi through SPI communication. Then, we connect a camera to the CSI head of the Raspberry Pi. We can turn on the smart multiple-tap for a certain period of time, or we can schedule the multi-tap to turn on at a specific time. To reduce standby power, people usually pull out a power code from multiple-taps or turn off a switch. Our method helps people do the same thing with a smart phone, if they are away from home.