• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.695-698
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• 1998

Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.

• Transactions on Electrical and Electronic Materials
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• 제15권3호
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• IT SoC Magazine
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• 통권19호
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• pp.37-42
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• 2007

이 글은 당사에서 개발 진행한 TDMB,ISDB-T등의 Moblie TV Receiver단의 Analog Front-End SIP들의 Test H/W, S/W제작 경험을 바탕으로 보다 효율적이고 성공적인 SIP 개발이 될 수 있도록 도움을 주고자 기술 하였다.

• Journal of information and communication convergence engineering
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• 제18권4호
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• pp.254-259
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• 2020

Phased-array antennas comprise a demanding antenna design methodology for commercial wireless communication systems or military radar systems. In addition to these two important applications, the phased-array antennas can be used in beamforming for wireless charging. In this study, a four-way analog beamforming front-end module (FEM) for a hybrid beamforming system is developed for 2.4 GHz operation. In a hybrid beamforming scheme, an analog beamforming FEM in which the phase and amplitude of RF signal can be adjusted between the RF chain and phased-array antenna is required. With the beamforming and beam steering capability of the phased-array antennas, wireless RF power can be transmitted with high directivity to a designated receiver for wireless charging. The four-way analog beamforming FEM has a 32 dB gain dynamic range and a phase shifting range greater than 360°. The maximum output RF power of the four-way analog beamforming FEM is 40 dBm (=10 W) when combined the four individual RF paths are combined.

• 한국수산과학회지
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• 제44권1호
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• pp.31-36
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• 2011

This study developed a normal temperature-circulatable retort-sterilized crab analog (RSCA) with a long shelf-life by retort sterilization. We examined the optimum sterilization conditions and quality characteristics of the RSCA. A central composite design for response surface methodology (RSM) was adopted to optimize of the retort sterilization. The central composite design consisted of 11 samples: four factorial points, four star points, and three central points. The sterilization temperature and $F_0$-value for retort sterilization were the independent variables, and the shearing force, whiteness, and sensory score for texture were the dependent variable. The RSM analysis of the multiple response optimization for the RSCA using the Minitap statistical programing gave an $F_0$-value of 3.3 min. at $117.5^{\circ}C$. The RSM analysis also indicated that the sterilization temperature during retort sterilization was the most influential factor, while the $F_0$-value had little effect on the quality of the RSCA. The moisture, pH and volatile basic nitrogen contents of the RSCA product were 73.1%, 7.3 and 17.2 mg/100 g, respectively, and viable cells count was >18 CFU/g. And sensory quality characteristics of this RSCA was similar to those of a commercial crab analog.

• 디지털융복합연구
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• 제19권6호
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• pp.315-321
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• 2021

본 연구는 인쇄매체가 영상매체로 재매개 되면서 콘텐츠가 변화되는 과정을 분석한다. 미디어를 통해 콘텐츠가 생산되고, 기존의 콘텐츠가 새로운 미디어에 흡수되면서 변화하는 과정을 관찰하여 재매개된 미디어의 특성을 파악한다. 재매개의 이중논리를 적용하여, 인쇄매체가 영상매체로 재매개되는 과정을 분석하고, 그 결과를 통해 매체의 변화와 변용을 이용한 재매개 방식이 디자인에 방법론에 적용될 수 있다는 가능성을 제시한다. 마블 코믹스는 마블 시네마틱 유니버스로 재매개 되었다. 아날로그 미디어가 새로운 미디어로 재매개되는 현상을 이해함으로써, 디자이너가 디자인을 할 때 재매개의 특성을 이용하여 결과물을 도출 할 수 있도록 디자인 방법론을 제시할 수 있다. 매체가 발달함에 따라 디자인의 범주도 넓어지고 있다. 본 연구를 통해 재매개를 이용한 디자인 방법론 제시되길 기대해 본다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.201-203
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• 2007

Safety critical systems are those in which a failure can have serious and irreversible consequences. Nowadays digital technology has been rapidly applied to critical system such as railways, airplanes, nuclear power plants, vehicles. The main difference between analog system and digital system is that the software is the key component of the digital system. The digital system performs more varying and highly complex functions efficiently compared to the existing analog system because software can be flexibly designed and implemented. The flexible design make it difficult to predict the software failures. This paper reviews safety standard and criteria for safety critical system such as railway system and suggests software development methodology for more detail description.