• Proceedings of the KSR Conference
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• 2011.10a
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• pp.3306-3311
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• 2011

Last Subway video surveillance system consists of a network device that is used. Through the network to transmit video data to digital conversion of analog video via a process server or a PC video to a split-screen in various forms is expressed. In recent years, multi-monitor video cameras from the same pop-up or more, such as history, structure expressed on a variety of video is required by express. The problem with these systems, video compression and transmission of many cameras, and this image data received from the server or PC to take out all the images you want to watch to occur when in order to express all of the images because of the need to decode most of the program per limit of number of channels is positioned. This limited number of channels to have a video that nothing forced, but it is likely to do so in the future performance of the hardware evolves gradually channeled images available number of channels will increase proportionately. However, as the development of hardware required for a single screen video channel will be more gradual capital. The hardware rather than relying solely on the performance of the decoded video data on the screen in order to express a more efficient utilization of shared memory for video surveillance software will provide the operating plan.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.89-91
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• 2004

In SCADA systems, an RTU is a device installed at a remote location that collects data, codes the data into a format that is transmittable and transmits the data back to a central station, or MTU. An RTU also collects information from the master device and implements processes that are directed by master device. RTUs are equipped with input channels for sensing or metering, output channels for control, indication or alarms and a communications port. In general, the data are transmitted via a wired communication infrastructure such as RS422 or RS485 between RTU and MTU. But, limited range of wired communication doesn't allow the system to cover remote areas over the limitation, and building a wired communication network is not easy in the circumstances. In this Paper, we design and implement a smart cost-effective Web-RTU that can communicate with MTU via Web. Web is of benefit to the Web-RTU, because it is not only free from the distance limitations, but also is built easily and cost-effectively wherever Internet resources are available. Additionally, Web can be easily applied to the SCADA system with the development of hardware and software for communications. The Web-RTU has a program memory, a data memory and a RAM inside, and uses Atmega128, low-cost 8 bit micro-processor with eight AI(Analog Input). It performs well enough to implement all existing roles of RTU.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.832-836
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• 2015

In this paper, a DC-DC converter is designed for logic process MTP (multi-time programmable) memory IPs using dual program voltage, which are used for analog trimming or storing chip IDs in sensor applications. The DC-DC converter supplies VPP (=5.25V), VNN (=-5.25V), and VNNL ($=2{\cdot}VNN/5$). It uses MOS capacitors and designed with only 3,3V devices. VPP and VNN are configured in two and five stages, respectively. And their pumping currents are $9.17{\mu}A$ and $9.7{\mu}A$, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.6
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• pp.691-697
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• 1999

This paper describes the implementation of a high speed image processing board. This image processing board is consist of a image acquisition part and a image processing part. The image acquistion part is digitizing the image input data from CIS and save it to the dual port RAM. By putting on the dual port memory between two parts, during acquistion of image, the image processing part can be effectively processing of large-volume image data. Most of all image preprocessing part are integrated in a large-scaled FPGA. We arwe using ADSP-2181 of the Analog Device Inc., LTD. for a image processing part, and using the available all memory of DSP for the large-volume image data. Especially, using of IDMA exchanges the data with the external microprocessor or the external PC, and can watch the result of image processing and acquired image. Finally, we show that an implemented image processing board used for the simulation of image retreval by the one of the typical application.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.310-318
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• 2015

In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.744-747
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• 1997

High performance digital computer technology enables the digital computer-based controllers to replace traditional analog controllers used for factory automations. This replacement, however, brings up the side effects caused by discrete quantization and non-real-time execution of control softwares. This paper describes the structure of real-time simulator and controller that can be used for design and verification of real-time digital controllers. The virtual machine concept adopted by real-time simulator make the proposed simulator be independent from the specific hardware platforms. The proposed system can also be used in the loosely coupled distributed environments connected through local area network using real-time message passing algorithm and virtual data table based on the shared memory mechanism.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.1
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• pp.115-121
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• 1999

Advanced digital computer technology enables the computer-based controllers to replace the traditional analog controllers used in factory automations. This replacement, however, brings up the side effects caused by the quantization error and non-real-time execution of control software. This paper describes the structure of real-time simulator and controller that can be used for design and verification of real-time digital controllers. The virtual machine concept adopted by the proposed real-time simulator makes the proposed simulator be independent from the specific hardware platforms. The proposed system can also be used in the loosely coupled distributed environments connected through local area network using real-time message passing algorithm and virtual data table based on the shared memory mechanism.