• Title/Summary/Keyword: Analog Memory

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Design of an Image Processing Board Using DSP(TMS320C6211) and Its Applications (DSP(TMS320C6211)를 이용한 영상 처리 보드의 설계 및 응용)

  • 박무열;최중경;구본민;류한성;권정혁;하홍수;김진애
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.227-230
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    • 2002
  • In this paper, we designed and made an image processing board that converts analog NTSC CVBS from CCD camera into digital image, stores it in a memory and accomplishes an appropriate digital image processing suitable to our application. And then loaded it on the self-controlled mobile vehicle and verified its performance by controlling the self-controlled mobile vehicle to avoid obstacles and arrive at the destination through various digital image processes. From the result, the self-controled mobile vehicle system avoided obstacles and got the destination correctly. We knew that designed image processing board is enough to realize the real-time control system.

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The Design and Implementation of a TV Tuner for the Digital Terrestrial Broadcasting

  • Chong, Young-Jun;Kim, Jae-Young;Lee, Il-Kyoo;Choi, Jae-Ick;Oh, Seung-Hyeub
    • Journal of electromagnetic engineering and science
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    • v.1 no.2
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    • pp.131-138
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    • 2001
  • The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

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A Study on the Linearity Synapse Transistor of Analog Memory Devices in Self Learning Neural Network Integrated Circuits (자기인지 신경회로망에서 아날로그 기억소자의 선형 시냅스 트랜지스터에 관한연구)

  • 강창수
    • Electrical & Electronic Materials
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    • v.10 no.8
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    • pp.783-793
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    • 1997
  • A VLSI implementation of a self-learning neural network integrated circuits using a linearity synapse transistor is investigated. The thickness dependence of oxide current density stress current transient current and channel current has been measured in oxides with thicknesses between 41 and 112 $\AA$, which have the channel width $\times$ length 10 $\times$1${\mu}{\textrm}{m}$, 10 $\times$ 0.3${\mu}{\textrm}{m}$ respectively. The transient current will affect data retention in synapse transistors and the stress current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the drain source current.

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A Study on the Characteristics of Synaptic Multiplication for SONOSFET Memory Devices (SONOSFET 기억소자의 시랩스 승적특성에 관한 연구)

  • 이성배;김병철;김주연;이상배;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.11a
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    • pp.1-4
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    • 1996
  • EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

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CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control (링 오실레이터를 가진 CMOS 온도 센서)

  • Kim, Chan-kyung;Lee, Jae-Goo;Kong, Bai-Sun;Jun, Young-Hyun
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.485-486
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    • 2006
  • This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

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Design of Expandable 32x32 MBAM Neuro-chip (확장 가능한 32X32 MBAM Neuro-chip의 설계)

  • 최윤경;박정배;이수영
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.6
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    • pp.86-92
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    • 1993
  • In this paper, we present a VLSI chip design of Multi-layer Bidirectionsl Associative Memory with good error-correction performance. The MBAM neural chip utilizes inner product implementation schems with binary storage and analog calculation.. Multi-layer can be constructed by direct cascading of these chips, and the number of neurons is expandable by parallel connection of these chips. We made proto-type chips and interface board to test the expansion. Currently the Chip has 32 input nodes, 32 output nodes, and can store up to 48 patterns, 32x48x2 SRAMs are included in the chip.

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1Kbit single-poly EEPROM IC design (1Kbit single-poly EEPROM IC 설계)

  • Jung, In-Seok;Park, Keun-Hyung;Kim, Kuk-Hwan
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.249-250
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    • 2008
  • In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.

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A Study on the Automatic Test Strategy of the Electronic Circuit Board Using Artificial Intelligence (인공지능기법을 이용한 전자회로보오드의 자동검사전략에 대한 연구)

  • 고윤석
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.12
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    • pp.671-678
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    • 2003
  • This paper proposes an expert system to generate automatically the test table of test system which can highly enhance the quality and productivity of product by inspecting quickly and accurately the defect device on the electronic circuit board tested. The expert system identifies accurately the tested components and the circuit patterns by tracing automatically the connectivity of circuit from electronic circuit database. And it generates automatically the test table to detect accurately the missing components, the misplaced components, and the wrong components for analog components such as resistance, coil, condenser, diode, and transistor, based on the experience knowledge of veteran expert. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. And, the validity of the builded expert system is proved by simulating for a typical electronic board model.

Development of Millimeter wave Radar System for an Automobile (차량용 밀리파 레이더 시스템의 개발)

  • 박홍민;이규한;최진우;신천우
    • Proceedings of the IEEK Conference
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    • 2001.06e
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    • pp.25-28
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    • 2001
  • This paper introduce a millimeter-wave radar system. As Fig 1 shows, This system consists of millimeter-wave radar front-end and digital signal processing parts through receive waves regarding up-coming obstacles. The system works as follow process; (1) Generate regular tripodal waves using the FMCW pulse generator (2) Transmit/Receive waves regarding up-coming obstacles (3) Analog filtering (4) FIFO memory interface (5) FFT(Fast Fourier Transform) (6) Calculation of distance / speed between cars (7) Object display and calibration. We have progress to solve the problem like as increase of traffic accidents causing damage and injuries due to the increased number of motor vehicles and long distance driving, and Need for a device to help drivers who are in trouble due to bad weather conditions. We are expect to Take the lead as a core technology in the ITS industry and to develop circuit and signal processing technologies related to millimeter-wave bandwidth.

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CMOS binary image sensor with high-sensitivity metal-oxide semiconductor field-effect transistor-type photodetector for high-speed imaging

  • Jang, Juneyoung;Heo, Wonbin;Kong, Jaesung;Kim, Young-Mo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.5
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    • pp.295-299
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    • 2021
  • In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.