• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.114-114
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(f0= 100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPIC simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.466-471
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• 2004

This paper proposes an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. 1-Pixel Fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of IKEEE
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• v.19 no.4
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.1114-1119
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(fo=100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of Sensor Science and Technology
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• v.30 no.5
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.