• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.65-70
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• 2006

An image sensor has limited dynamic range while the human eye has logarithmic response over wide range of light intensity. Although the sensor gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye response. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This Paper proposes a CMOS image sensor (CIS) with a nonlinear analog-to-digital converter (AU) which performs analog gamma correction. The CIS with the proposed nonlinear analog-to-digital conversion scheme was fabricated with a $0.35{\mu}m$ CMOS process. The analog gamma correction using the proposed nonlinear ADC CIS provides the 2.2dB peak-signal-to-noise-ratio(PSM) improved image qualify than conventional digital gamma correction. The PSNR of the image obtain from the digital gamma correction is 25.6dB while it is 27.8dB for analog gamma correction. The PSNR improvement over digital gamma correction is about $28.8\%$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• Journal of the Korea Society for Simulation
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• v.11 no.2
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• pp.17-29
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• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1003-1006
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• 2003

본 논문에서는 sub-micron 소자에서 SCE(Short Channel Effect) 억제를 위한 Halo 와 SSR(Super Steep Retrograde Well) 적용에 따른 analog 특성의 열화를 석하고 이를 개선하기 위해 Twist 이온주입과 In, Sb Halo 를 채택하였다. Analog 특성은 CMOS 의 amplifier 과 Comparator 로의 사용을 고려해 Drain Rout과 Early voltage를 이용해 나타내었으며 Digital 성능을 함께 고려하였다. 실험결과 NMOS 의 경우 45 twist Halo 조건에서, PMOS의 경우 As보다 Sb를 Halo 로 적용하는 경우 더 우수한 analog 특성을 나타내었다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.28-35
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• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.