• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2485-2492
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• 2018

The rapid development of large-scale integrated circuits has brought great challenges to the circuit testing and diagnosis, and due to the lack of exact fault models, inaccurate analog components tolerance, and some nonlinear factors, the analog circuit fault diagnosis is still regarded as an extremely difficult problem. To cope with the problem that it's difficult to extract fault features effectively from masses of original data of the nonlinear continuous analog circuit output signal, a novel approach of feature extraction and dimension reduction for analog circuit fault diagnosis based on wavelet packet decomposition, local linear embedding algorithm, and clone selection algorithm (WPD-LLE-CSA) is proposed. The proposed method can identify faulty components in complicated analog circuits with a high accuracy above 99%. Compared with the existing feature extraction methods, the proposed method can significantly reduce the quantity of features with less time spent under the premise of maintaining a high level of diagnosing rate, and also the ratio of dimensionality reduction was discussed. Several groups of experiments are conducted to demonstrate the efficiency of the proposed method.

• Journal of the Korea Society of Computer and Information
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• v.23 no.2
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• pp.27-34
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• 2018

In this paper, we propose a new method to read the hand of analog gauges to prepare for the smart factory. In addition, we suggest a new and improved method that can apply, in general, diverse analog gauges even if their scale types and ranges are various. Many companies are making great efforts to build smart factories that increase energy efficiency and automation. Managers use a variety of equipment and tools to manage the production process at the factory. In this kind of factory, analog gauges have been often used with many equipment and tools. Analog gauges are mostly circular in shape, and most papers use circular hough transform to find the center and radius of a circle. However, when the object to be found is not of the correct circle type, it takes a long time to recognize the circle using the circular hough transform, and the center and radius of the circle can not be calculated accurately. The proposed method was tested on various circular analog gauges. As a result, we confirmed that our method is outstanding.

• Journal of Convergence for Information Technology
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• v.9 no.9
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• pp.38-43
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• 2019

In this paper, a method of inputting one analog input and two digital switch inputs by using one analog port of microcontroller embedded in IoT device was proposed. In this method, the upper limit and the lower limit of the input voltage range of the analog input port are determined, and the analog input voltage is input to this interval. The digital switches are configured to exceed the boundaries of the upper and lower limits, respectively. To verify the performance of the proposed method, an experimental circuit was constructed and tested using a microcontroller. As a result, all three inputs can be sensed using a single analog port, thus confirming that the three required input ports are reduced to one input port, ie, 33%.

• Current Optics and Photonics
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• v.4 no.6
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• pp.483-499
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• 2020

In this paper, a novel analog signature scheme is proposed by modifying an RSA-based digital signature scheme with optical phase-shifting digital holography. The purpose of the proposed method is generating an analog signature to provide data confidentiality and security during the data transfer, compared to the digital signature. The holographic encryption technique applied to a hash value reveals an analog-type of pseudo-random pattern in the analog signature scheme. The public key and secret key needed to verify the analog signature are computed from public key ciphers which are generated by the same holographic encryption. The proposed analog signature scheme contains a kind of double encryption in the process of generating signature and key, which enhances security level more than the digital signature. The results of performance simulations show the feasibility of the highly secure signature scheme, and security analysis shows high robustness against known-message attacks and chosen-message attacks. In addition, the proposed method can apply to one-time signature schemes which can be used to sign only one message and it can also apply to authentication, e-mails, electronic banking and electronic data interchange.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.149-152
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• 2002

The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1229-1232
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• 2003

In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The simulation result show that the proposed Analog-to-Digital Converter can be operated at 40Ms/s with 8-bit resolution and INL/DNL errors are +0.4LSB~-0.6LSB / +0.9LSB~-1.4LSB , respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.193-196
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• 2001

For wide locking range, an analog delay locked loop (DLL) was designed with the selective phase inversion scheme and the variable number of delay elements. The number of delay elements was determined adaptively depending on the clock cycle time. During the analog fine locking stage, a self-initializing 3-state phase detector was used to avoid the initial state problem associated with the conventional 3-state phase detector. With these schemes, the locking range of analog DLL was increased by four times compared to the conventional scheme according to the simulation results.