• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1304-1308
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• 2005

This paper presents the case that the existing analog control systems were retrofitted with digital DCS(Distributed Control System)s for boiler unit in thermal power plant. Replacement of existing worn-out or obsolete analog control systems has been considered. Replacement of existing analog control systems with another analog control systems has lots of difficulties in maintaining the systems due to being out of stock. Due to those difficulties, existing analog control systems have been retrofitted with digital DCSs in many industrial sites. KEPRI(Korea Electric Power Research Institute) accomplished the project that retrofitted analog control systems with the developed DCSs for boiler unit in middle-scale coal-fired thermal power plant. The benefits of an upgrade to digital control include a increase of reliability due to system redundancy, ease of modifying the control logic and the parameters of function block, ease of maintenance due to available spare parts, improvement of information display, ease of modifying MMI(Man Machine Interface) displays, a increase in system availability, and improvement of control performance. This paper describes how to use the parameters of existing analog controllers, the implementation of digital PID controller, control system configuration for boiler unit in thermal power plant, some boiler control loops, control result during commissioning, and the comparison of boiler characteristic test data after retrofitting with the existing test data.

• Journal of Biosystems Engineering
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• 제22권2호
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• pp.117-126
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• 1997

A series of soil bin experiment was carried out on sandy loam to investigate if it is possible to predict implement draft by some analog tool. Chisel configuration resembling a cone penetrometer section was used as an analog tool. The angle of cone was 30 degree. Three types of tillage implement, or oriental janggi, moldboard plow and chisel plow were chosen for this study. Experimental tillage speed was 0.22, 0.33, 0.49 m/s ad tillage depth was 8, 12, 16cm. For the experimental tillage speed range, the increase of tillage speed did not affect the tillage draft for the three types of implement and analog tool, but as the tillage depth increased, tillage draft of the three types of implement and analog tool increased linearly. The linear relationship was found between the tillage draft of analog tool and that of three types of tillage implement for the experimental tillage depth and speed range with high value of $R^2$ Thus it was concluded from the above results that an analog tool can be used to predict the tillage draft of oriental janggi, moldboard plow and chisel plow. But more experiment for various soil types and theoretical verification are needed for more generallization.

• 전기학회논문지P
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• 제58권4호
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.8-12
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• 2002

Since the high performance analog-to-digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Sng1e Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• 전자공학회논문지C
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• 제35C권9호
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• pp.57-63
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• 1998

본 논문에서는 새로운 디지털-아날로그 변환알고리즘을 적용한 CMOS 디지털-아날로그 변환기를 개발하였다. 이 변환기를 1.2㎛ MOSIS SCMOS 파라미터로 설계하여 시뮬레이션으로 그 성능을 확인해 본 결과 200MHz의 최대변환속도와 7.41mW의 DC 소모전력을 나타내었고 8-b에서 각각 ±0.008LSB의 INL(integral nonlinearity)과 ±0.098LSB의 DNL(differential nonlinearity)를 나타내었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• Journal of information and communication convergence engineering
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• 제18권4호
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• pp.254-259
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• 2020

Phased-array antennas comprise a demanding antenna design methodology for commercial wireless communication systems or military radar systems. In addition to these two important applications, the phased-array antennas can be used in beamforming for wireless charging. In this study, a four-way analog beamforming front-end module (FEM) for a hybrid beamforming system is developed for 2.4 GHz operation. In a hybrid beamforming scheme, an analog beamforming FEM in which the phase and amplitude of RF signal can be adjusted between the RF chain and phased-array antenna is required. With the beamforming and beam steering capability of the phased-array antennas, wireless RF power can be transmitted with high directivity to a designated receiver for wireless charging. The four-way analog beamforming FEM has a 32 dB gain dynamic range and a phase shifting range greater than 360°. The maximum output RF power of the four-way analog beamforming FEM is 40 dBm (=10 W) when combined the four individual RF paths are combined.

• ETRI Journal
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• 제44권5호
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.