Improvement of Time-Delay of the Analog Viterbi Decoder through Minimizing Parasitic Capacitors in Layout Design

아날로그 비터비 디코더에 있어서 기생 cap성분 최소화 layout 설계에 의한 신호전파 지연 개선

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.