• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.1-6
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• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• Journal of IKEEE
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• v.19 no.1
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• pp.45-51
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• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.250-252
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• 2017

블록암호 국제표준 AES(Advanced Encryption Standard), 국내표준 ARIA(Academy, Research Institute, Agency) 및 국제표준 해시함수 Whirlpool을 통합 하드웨어로 구현하였다. ARIA 블록암호와 Whirlpool 해시함수는 AES와 유사한 구조를 가지며, 본 논문에서는 저면적 구현을 위해서 하드웨어 자원을 공유하여 설계하였다. Verilog-HDL로 설계된 ARIA-AES-Whirlpool 통합 보안 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 20 MHz의 동작 주파수에서 71,872 GE로 구현되었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.837-840
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• 2007

Recently, Not only PC environment but also movile environment using XML for translating data. But the mobile delevopment is more limited but need highler security than PC environment Because there is some important service such as mobile banking. In this paper, We development the system to encrypt and decrypt the XML data in order to protect data, And the system is observing the recommendation of the XML Encryption Syntax and Processing by W3C. When encrypting the data, We use the entryption algorithm DES, Triple-DES, AES, SEED and RSA. and consideration of the mobile environment Last, We test the system at WIPI environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.264-271
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• 2021

From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.11-19
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• 2020

Modern GPU can execute general purpose computation on the graphic processing unit, and provide high performance by exploiting many core on GPU. To run AES algorithm efficiently, parallel computational resources are required. However, computational resource of CPU architecture are not enough to cryptographic algorithm such as AES whereas GPU architecture has mass parallel computation resources. Therefore, this paper reduce the time to execute AES by employing parallel computational resource on GPGPU. Unfortunately, AES cannot utilize computational resource on GPGPU since it isn't suitable to GPGPU architecture. In this paper, IPC based dynamic SM management technique are proposed to efficiently execute AES on GPGPU. IPC based dynamic SM management can increase and decrease the number of active SMs by using IPC in run-time. According to simulation results, proposed technique improve the performance by increasing resource utilization compared to baseline GPGPU architecture. The results show that AES improve the performance by 41.2% on average.

• Journal of IKEEE
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• v.24 no.3
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• pp.791-796
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• 2020

In this paper, "Q-Bone", a 3^rd generation blockchain platform with enhanced security and flexibility, was developed. As a 3^rd generation blockchain platform, it exploits BP (block producer) to increase processing speed. It has many advantages as follows. It improves both security and speed by mixing RSA (Rivest-Shamir-Adleman) and AES (advanced encryption standard). It improves flexibility by exploiting gateway to convert between apps and blockchain with different programming language. It increases processing speed by combining whole transactions into one block and distribute it when too many transactions occur. It improves search speed by inserting sequence hash into transaction data. It was implemented and applied to pet communication service and academy-instructor-student matching service, and it was verified to work correctly and effectively. Its processing speed is 3,357 transactions/second, which shows excellent performance.