• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.78-86
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• 2003

When we transformed from Monochrome-data to Color-data in text mode, we used hardware-method to design the circuit which is convertible in real time. We saved color information in every screens that can make screen in Color Palette ROM and it is also generated 8bit. lower 4bit assign foreground color and upper 4bit can design to have background color. We have Address Reduction ROM to remove repeated address and reduce volume of Color Palette ROM to 1/16. Besides, we have many D-FF to save address, data and page information temporarily after that, we have management process 8 times through counter in real time. Finally, we chose either foreground color or background color in multiplex and established color information was sended to the color video controller. Thus, you can use it as a good interface when yow transfer many control devices with Monochrome display (ex, LCD Monitor) into devices with Color display.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.192-198
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). To reduce the ROM size, we use the differential quantization technique with this two ROM. First, we quantize the quarter sine wave with the $2^L$ address and store the quantized value at the Q-ROM. Second, after the $2^L$ address are equally divided into $2^M$ sampling intervals, the sampling value is quantized. And the D-ROM store only the difference between this quantized value and the Q-ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.18-21
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• 2009

In the digital system, ROM has a large power-consumption and a speed-bottleneck. According to gradual growth of system speed, ROM is demanded to have low-power consumption and high-speed operation design. The ROM adapted in FFT or FIR filter needs method of sequential accessed addressing. We proposed a reduction method for the number of storage cells in this paper. The number of storage cells which is connected with bi-line is reduced by the proposed method so that the capacitance value of bit-time is reduced. In this case, delay time, and power consumption are reduced. Design result of ROM in this paper using the proposed method could reduce up to 86.3% of storage cell '1' compare with conventional method.