• Journal of Astronomy and Space Sciences
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• v.34 no.4
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• pp.281-288
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• 2017

The first Korea lunar orbiter, Korea Pathfinder Lunar Orbiter (KPLO), has been in development since 2016. After launch, the KPLO will execute several maneuvers to enter into the lunar mission orbit, and will then perform lunar science missions for one year. Among these maneuvers, the lunar orbit insertion (LOI) is the most critical maneuver because the KPLO will experience an extreme velocity change in the presence of the Moon's gravitational pull. However, the lunar orbiter may have a delayed LOI burn during operation due to hardware limitations and telemetry delays. This delayed burn could occur in different captured lunar orbits; in the worst case, the KPLO could fly away from the Moon. Therefore, in this study, the burn delay for the first LOI maneuver is analyzed to successfully enter the desired lunar orbit. Numerical simulations are performed to evaluate the difference between the desired and delayed lunar orbits due to a burn delay in the LOI maneuver. Based on this analysis, critical factors in the LOI maneuver, the periselene altitude and orbit period, are significantly changed and an additional delta-V in the second LOI maneuver is required as the delay burn interval increases to 10 min from the planned maneuver epoch.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.155-159
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• 2001

In this paper, an on-line dead-time compensation method based on a time delay control approach is presented. The disturbance voltages caused by the dead time are estimated in an on-line manner by the time delay control without any additional circuits and off-line experimental measurements. And the estimated disturbance voltages are fed to voltage references in order to compensate the dead-time effects. The proposed method is applied to a PM synchronous motor drive system and implemented by using software of a digital signal processor (DSP) TMS320C31. Experiments are carried out for this system and the results well demonstrate the effectiveness of the proposed method.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1840-1841
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• 2006

Plants with long time-delays can not be often controlled effectively using a simple PID controller. The main reason for this is that the additional phase lag contributed by the time-delay tends to destabilize the closed-loop system. The stability problem can be solved by smith predictor. However, in this case responses are very sensitive to the estimated model errors. To reduce sensitive problem, this paper is presented based on virtual reference feedback tuning of the time delay plant using the closed-loop test to find parameters for a PID controller using the closed-loop test data.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.321-324
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• 2002

Nowadays variable delay arithmetic units have been used for implementing a datapath of\ulcorner target system in pursuit of performance improvement. However. adoption of variable delay arithmetic units requires modification of a typical synchronous control units design methodology. There is a representative approach, which is called a monolithic approach. Although its results are good, its proposed methodology may cause critical problems in the aspects of area and performance with the size increase of initial system specifications. In order to solve this problems, a distributed approach is suggested. Experimental results show that the Proposed method can guarantee original performance of an initial system specification with minimized additional area increase.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• Journal of applied mathematics & informatics
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• v.40 no.3_4
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• pp.603-618
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• 2022

In this paper, a numerical solution of the generalized diffusion equation with a delay has been obtained by a numerical technique based on the Galerkin finite element method by applying the cubic B-spline basis functions. The time discretization process is carried out using the forward Euler method. The numerical scheme is required to preserve the delay-independent asymptotic stability with an additional restriction on time and spatial step sizes. Both the theoretical and computational rates of convergence of the numerical method have been examined and found to be in agreement. As it can be observed from the numerical results given in tables and graphs, the proposed method approximates the exact solution very well. The accuracy of the numerical scheme is confirmed by computing L₂ and L_∞ error norms.

• Bulletin of the Korean Mathematical Society
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• v.61 no.1
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• pp.229-246
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• 2024

We consider the delay differential equations $$b(z)w(z+1)+c(z)w(z-1)+a(z)\frac{w'(z)}{w^k(z)}=\frac{P(z, w(z))}{Q(z, w(z))}$$, where k ∈ {1, 2}, a(z), b(z) ≢ 0, c(z) ≢ 0 are rational functions, and P(z, w(z)) and Q(z, w(z)) are polynomials in w(z) with rational coefficients satisfying certain natural conditions regarding their roots. It is shown that if this equation has a non-rational meromorphic solution w with hyper-order ρ2(w) < 1, then either deg_w(P) = deg_w(Q) + 1 ≤ 3 or max{deg_w(P), deg_w(Q)} ≤ 1. In addition, it is shown that in the case max{deg_w(P), deg_w(Q)} = 0 the equations above can have such a solution, with an additional zero density requirement, only if the coefficients of the equation satisfy certain strict conditions.

• The KIPS Transactions:PartC
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• v.10C no.3
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• pp.367-376
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• 2003

This study deals with the DCMST (Delay constrained Capacitated Minimum Spanning Tree) problem applied in the topological design of local networks or finding several communication paths from root node. While the traditional CMST problem has only the traffic capacity constraint served by a port of root node, the DCMST problem has the additional mean delay constraint of network. The DCMST problem consists of finding a set of spanning trees to link end-nodes to the root node satisfying the traffic requirements at end-nodes and the required mean delay of network. The objective function of problem is to minimize the total link cost. This paper presents two-phased heuristic algorithm, which consists of node exchange, and node shift algorithm based on the trade-off criterions, and mean delay algorithm. Actual computational experience and performance analysis show that the proposed algorithm can produce better solution than the existing algorithm for the CMST problem to consider the mean delay constraint in terms of cost.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.570-576
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• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.