• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.784-786
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• 2000

This paper implements and analyzes logically the Borrow Look-ahead Subtracter using Borrow Generator and Borrow Propagator. In subtracting calculation, we improve the calculating efficiency with using 4-bit subtracter which has Borrow Look-ahead Subtracters connection, and show that this is compatible with adder using the concept of Carry Generator and Carry Propagator. This subtracter may be useful in frequent subtracting calculation. We think this approach makes it possible to implement simple ALU(Arithmetic Logic Unit) with combining the concept of Borrow Look-ahead Subtracter and Carry Look-ahead Adder.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.59-66
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• 2000

본 논문에서는 DSP에서 필수적인 고속 저 전력 조건 선택 덧셈기/뺄셈기의 마크로 셀 라이브러리를 설계, 구축하였다. 덧셈기의 Carry전달 지연 시간을 최소로 하기 위한 CLA 기법과 연산 가능한 모든 결과 값을 미리 계산한 후 선택하는 조건 선택 기법을 적용하였다. 또한 이러한 설계방법이 8비트에서 64비트까지 자동 생성될 수 있도록 전용 프로그램을 작성하고 셀 기반 설계기법을 도입하여 Auto P&R Tool과 연계하여 자동으로 레이아웃이 가능하도록 하였다. 제안된 덧셈기/뺄셈기는 0.25${\mu}m$, 1-Poly, 5-Metal, N-well CMOS 공정을 사용하여 제작되었으며, 2.5V 단일 공급전압에서 지연시간, 소모 전력을 측정하였다. 측정결과 32 비트 덧셈기/뺄셈기의 경우 3.43ns의 지연시간과 42.8${\mu}w$/MHz의 전력소비를 나타내었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• 대한전자공학회논문지SD
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• 제45권1호
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• pp.1-6
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• 2008

이진수 시스템에서는 하드웨어 구현, 연산속도 등에 따라 음수와 양수를 나타내는 여러 가지 수 표현법이 있다. 그 중에서 한 비트로 부호를 정하고 나머지 비트들로 절대값을 표현하는 부호화-절대값 표현법은 간단하고 부호비트를 변환 시키는 것만으로 음수를 구할 수 있다. 그러나 부호화-절대값 표현법에서 실제 계산은 연산과 연산자들의 부호에 따른 절대값 비교를 필요로 한다. 간단한 구조에서 두 부호화-절대값 수의 덧셈, 뺄셈 연산기는 비교기와 선택적인 보수기, 덧셈기로 구성된다. 본 논문에서는 명시적인 비교기 사용 없이 두 수의 차이를 구할 수 있는 회로를 설계하고 이 회로를 이용하여 두 부호화-절대값으로 표현되는 수의 덧셈/뺄셈을 수행하는 가/감산기 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• 전자공학회논문지CI
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• 제40권6호
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• pp.32-38
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• 2003

인간 친화적인 10진 계산을 위한 3초과 십진 가·감산기 회로를 제안한다. 십진 회로를 이용한 계산 시속도 문제는 carry lookahead (CLA) 회로를 이용하여 해결할 수 있다. 제안하는 3초과 십진수 가산기 설계에서는 CLA와 함께 보정회로 및 변환회로를 개선함으로서 지연시간을 줄일 수 있다. 3초과 코드를 사용함으로서 감산과정에서 가산기만을 사용하여 계산을 할 수 있다 이 3초과 십진 가ㆍ감산회로는 기존의 설계에 비하여 상당한 속도 개선효과를 얻게 해준다.

• 정보과학회지
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• 제3권1호
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• pp.18-30
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• 1985

三値논리는 同一의 情報量을 表現하는데 二値에 비하여 적은수의 記號로 써 達成할 수 있고 演算速度가 빠르다는 특징을 갖고 있다. 그러나 현재로서는 回路素子가 三値論理에 適合한 것이 나와 있지 않고 二値論理만큼 工學的인 接近 이 이루어져 있지 않은 상태이지만 보다 고 속의 情報處理裝置를 構成하기 위해 서 이 分野의 硏究는 價値있는 일이라 하겠다. 三値論理에 對해서는 Post(1),, M hldorf(2) 이래 많은 硏究가 있었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1012-1015
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. The adjust parameter of PID to achieve best response of process which be using time and may be error if user are not expert. Nowadays this problem was solved by develop PID controller which can analysis and auto tune parameter are appropriate with process which used principle of Ziegler ? Nichols but it are expensive and designed for each task. Thus, this paper proposes auto tune PID based on FPGA by use principle of Dahlin which maximum overshoot not over 5 percentages and do not fine tuning again. It have performance in control process are neighboring controller in industrial and simple to use. Especially, It can use various process and low price. The auto tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. It was verified by control model of temperature control system.

• 대한전자공학회논문지
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• 제27권6호
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• pp.910-920
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• 1990

This paper presents a method of constructing an Arithmetic Operation Unit Systems (A.O.U.S.) over Galois Field GF(2**m) for the purpose of the four arithmetical operation(addition, subtraction, multiplication and division between two elements in GF(2**mm). The proposed A.O.U.S. is constructed by following procedure. First of all, we obtained each four arithmetical operation algorithms for performing the four arithmetical operations using by mathematical properties over GF(2**m). Next, for the purpose of realizing the four arithmetical unit module (adder module, subtracter module, multiplier module and divider module), we constructed basic cells using the four arithmetical operation algorithms. Then, we realized the four Arithmetical Operation Unit Modules(A.O.U.M.) using basic cells and we constructd distributor modules for the purpose of merging A.O.U.M. with distributor modules. Finally, we constructed the A.O.U.S. over GF(2**m) by synthesizing A.O.U.M. with distributor modules. We prospect that we are able to construct an Arithmetic & Logical Operation Unit Systems (A.L.O.U.S.) if we will merge the proposed A.O.U.S. in this paper with Logical Operation Unit Systems (L.O.U.S.).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.