• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.617-630
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• 2010

At 37th VCEG meeting in Jan. 2009, Toshiba proposed Quadtree-based Adaptive Loop Filter (QALF). The basic concept of QALF is to apply Wiener filter to decoded image after the conventional deblocking filter and to represent the filter on/off flag data for each basic filtering unit in a more efficient way of quadtree structure. QALF could enhance the compression performance of around more than 9%, but the structure of one filter for a decoded frame leaves room for further improvement in the sense that optimal filter for one region of a frame could quite different from the optimal filter for other parts of a picture. This paper proposes multiple adaptive loop filters for better utilization of local characteristics of decoded frame to optimize the region-based Wiener filters. Additional filters, proposed in this paper, cover separate spatial area of each decoded frame according to the performance of previously designed filter(s) to provide the flexibility of rate-distortion based selection of the number of filters.

• Journal of Broadcast Engineering
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• v.16 no.1
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• pp.1-13
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• 2011

In this paper, we propose an adaptive in-loop filter to improve the coding efficiency. Recently, there are post-filter hint SEI and block-based adaptive filter control (BAFC) methods based on the Wiener filter which can minimize the mean square error between the input image and the decoded image in video coding standards. However, since the post-filter hint SEI is applied only to the output image, it cannot reduce the prediction errors of the subsequent frames. Because BAFC is also conducted with a deblocking filter, independently, it has a problem of high computational complexity on the encoder and decoder sides. In this paper, we propose the low-complexity adaptive in-loop filter (LCALF) which has lower computational complexity by using H.264/AVC deblocking filter, adaptively, as well as shows better performance than the conventional method. In the experimental results, the computational complexity of the proposed method is reduced about 22% than the conventional method. Furthermore, the coding efficiency of the proposed method is about 1% better than the BAFC.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.146-150
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• 1989

In the pole assignment strategy, the closed loop poles are placed at prespecified locations. The amount of control effort required is to some extent proportional to the distance of the proposed closed loop locations of the poles from their open loop locations. The poor choice of closed loop locations may result in Large control effort and it may nuke the system unstable. To overcome this problem, pole shift control strategy is described in this paper. The validity of the proposed control strategy is assured through some simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.1
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• pp.105-122
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• 2011

The fundamental design goal of wireless sensor MAC protocols is to minimize unnecessary power consumption of the sensor nodes, because of its stringent resource constraints and ultra-power limitation. In existing MAC protocols in wireless sensor networks (WSNs), duty cycling, in which each node periodically cycles between the active and sleep states, has been introduced to reduce unnecessary energy consumption. Existing MAC schemes, however, use a fixed duty cycling regardless of multi-hop communication and traffic fluctuations. On the other hand, there is a tradeoff between energy efficiency and delay caused by duty cycling mechanism in multi-hop communication and existing MAC approaches only tend to improve energy efficiency with sacrificing data delivery delay. In this paper, we propose two different MAC schemes (ADS-MAC and ELA-MAC) using closed-loop control in order to achieve both energy savings and minimal delay in wireless sensor networks. The two proposed MAC schemes, which are synchronous and asynchronous approaches, respectively, utilize an adaptive timer and a successive preload frame with closed-loop control for adaptive duty cycling. As a result, the analysis and the simulation results show that our schemes outperform existing schemes in terms of energy efficiency and delivery delay.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.96-100
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• 2015

Adaptive background gain calibration loop for multi-lane serial links is proposed. In order to detect and cancel gain mismatches between lanes, a single digital loop using a ${\sum}{\Delta}$ ADC is employed, which provides a real-time adaptation of gain variations and is shared among all lanes to reduce power and area. Evaluation result showed that gain mismatches between lanes were well calibrated and tracked, resulting in timing budget at $10^{-6}$ BER increased from 0.261 UI to 0.363 UI with stable loop convergence.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.5
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• pp.475-483
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• 2002

The new architecture for the stabilization of an adaptive linearizer using the RLS algorithm is presented. The delay lock loop is apl)lied to compensate the feedback loop delay of the nonlinear amplifier output, and the Yang's algorithm is used to mitigate the numerical unstability of the RLS algorithm. This method is applied to the linearizer using the polynomial predistorter, and it's efficacy is verified by the simulation of the proposed structure.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.12
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• pp.1218-1225
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• 2008

This paper presents the design of a neural network based adaptive control for missile is presented. The application model is Exocet MM40, which is derived from missile DATCOM database. Acceleration of missile by tail Fin control cannot be controllable by DMI (Dynamic Model Inversion) directly because it is non-minimum phase system. So, the inner loop consists of DMI and NN (Neural Network) and the outer loop consists of PI controller. In order to satisfy the performances only with PI controller, it is necessary to do some additional process such as gain tuning and scheduling. In this paper, all flight area would be covered by just one PI gains without tuning and scheduling by applying mixture control technique of conventional controller and NN to the outer loop. Also, the simulation model is designed by considering non-minimum phase system and compared the performances to distinguish the validity of control law with conventional PI controller.

• Broadcasting and Media Magazine
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• v.24 no.4
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• pp.87-101
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• 2019

JVET(Joint Video Experts Team)에서 새로운 비디오 압축 표준으로 진행 중인 VVC(Versatile Video Coding)에서는 HEVC(High Efficiency Video Coding)의 기술을 근간으로 부호화 효율을 높일 수 있는 다양한 새로운 기술들을 채택하고 있다. 인루프 필터(In-Loop Filter)는 복원영상의 화질을 향상시키기 위한 기술로 주관적 화질 개선뿐만 아니라 부호화 효율을 향상시키는 기술로 기존 HEVC의 확장 기술 및 새로운 인루프 필터 기술을 채택하고 있다. 본 고에서는 VVC의 CD에 채택되어 있는 인루프 필터 기술들을 소개한다. 인루프 필터 기술은 HEVC에 채택되어 있는 디블록킹 필터(Deblocking Filter: DF)와 SAO(Sample Adaptive Offset), 새로이 추가된 ALF(Adaptive Loop Filter)의 3가지의 필터와 LMCS(Luma Mapping with Chroma Scaling) 기술을 포함하고 있다. 이들 인루프 필터 기술은 주관적 화질 개선과 부호화 효율을 크게 개선하고 있으며, 2020년 7월 FDIS(Final Draft International Standard) 완료를 앞두고 인루프 필터링의 다양화로 인한 성능과 복잡도를 고려한 간소화 및 병렬처리 등의 고속화에 대한 표준화가 지속적으로 이루어질 전망이다.