• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.23-28
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• 2007

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a strong point for easy implementation and extensibility. The proposed ATM switch fabric architecture is applicable to mobile communication, narrow band services over ATM network.

• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• 인터넷정보학회논문지
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• 제5권3호
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• pp.45-56
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• 2004

본 논문에서는 네트워크가 많은 endpoint를 가질지라도 낮은 비트율의 데이터를 효율적으로 전송할 수 있는 AAL 유형 2 스위치를 포함하는 ATM스위치 구조를 제안한다. 컴퓨터 프로그램으로 모델링한 ATM스위치는 AAL 유형 1, AAL 유형 2, AAL 유형 3/4 및 AAL 유형 5 셀로 이루어진 모든 유형의 AAL 셀에 대해 셀 스위칭을 지원하고 있다. 우리는 2가지 방식의 스위치를 제안하고 있는데, 하나는 개별적인 입력 포트마다 AAL 유형 2 셀 처리를 지원하는 스위치 패브릭이고, 다른 하나는 모든 입력 포트에 대한 전체적인 AAL 셀 처리를 지원하는 스위치 패브릭이다. 시뮬레이션 결과는 후자의 방식이 전자의 방식보다 우수한 것으로 나타났다. 그러나, 전자의 방식이 구현이 용이하고, 확장성에 대한 장점을 가지고 있다. 따라서 본 논문에서는 전자의 방식을 채용한 AAL 유형 2 스위치 모듈을 VHDL 언어를 사용하여 설계하였으며, 이를 FPGA로 구현하였다. 설계된 칩은 52MHz에서 동작하였다. 본 논문의 ATM 스위치 패브릭은 범용의 ATM 스위치 패브릭으로서 뿐만 아니라 ATM 네트워크상으로 모바일 통신, 협대역 서비스 및 무선 ATM등에 폭넓게 응용될 것으로 사료된다.

• 전자공학회논문지S
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• 제36S권10호
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• pp.40-50
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• 1999

서비스의 다양화, 고기능화, 고객의 요구에 부응하는 통신 네트워크에 대한 새로운 요구가 일어나고 있다. 따라서 ATM 전달망의 특징을 이용한 개방형 네트워크 구조에 대한 연구가 활발히 이루어지고 있다. 본 논문에서는 ATM 네트워크의 전달망을 스위치 네트워크로 이용하는 VSN(Virtual Switch Network) 개념을 IMT-2000 스위칭 시스템에 적용하고, 호 처리과정을 이용하여 VSN의 특성을 평가한다. 이 결과를 기본으로 VSN 기반 제어계 집약형 ATM-MSC 노드 구조를 제시하고, 호 처리 절차를 이용하여 VSN의 특성을 평가한다. 그 결과, 3.5msec 정도의 호 처리 지연을 허용하면, CCCP(Call and Connection Control Processor)를 중심으로 반경 100km내에서 VSN을 이용한 ATM-MSC 시스템 구성이 가능함을 나타낸다. 그리고 VSN 개념을 적용한 ATM-MSC 시스템 구성의 가능성과 VSN의 타당성을 분명히 한다.

• 경영과학
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• 제10권1호
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• pp.139-156
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• 1993

Various ATM switches have been proposed since Asynchronous Transfer Mode (ATM) was recognized as appropriate for implementing broadband integrated services digital network (BISDN). An ATM switching network may be evaluated on two sides : traffic performances (maximum throughput, delay, and packet loss probability, etc.) and structural features (complexity, i.e. the number of switch elements necessary to construct the same size switching network, maintenance, modularity, and fault tolerance, etc.). ATM switching networks proposed to date tend to show the contrary characteristics between structural features and traffic performance. The Knockout Switch, which is well known as one of ATM switches, shows a good traffic performance but it needs so many switch elements and buffers. In this paper, we propose an input and output buffered Knockout Switch for the purpose of reducing the number of switch elements and buffers of the existing Knockout Switch. We analyze the traffic performance and the structural features of the proposed switching architecture through a discrete time Markov chain and compare with those of the existing Knockout Switch. It was found that the proposed architecture could reduce more than 40 percent of switch elements and more than 30 percent of buffers under a given requirement of cell loss probability of the switch.

• 전자공학회논문지A
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• 제29A권7호
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• pp.19-30
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• 1992

In this paper, a new large scale ATM switch architecture for Broadband ISDN is presented and its performance is analyzed mathematically. The proposed two-stage ATM switch consists of a sorting network and several unit switches. The proposed switch is self-routing and nonlocking. Its maximum through put is 100% without speed up which other output buffered switch needs. The hardware complexity mainly depends on that of a sorting network, but sorting network is easy to be implemented to VLSI because of its regularity in the structure.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.113-116
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• 1999

This paper presents a hardware architecture of AAL(ATM Adaptation Layer) type 2 switch. The proposed architecture can assign and configure maximum AAL2 CID limit. AAL2 is the protocol which has been recommended by ITU-T and ATM-Forum for low bit rate delay sensitive services. The architecture assumes 155 Mbps STM-1/STS-3c physical interface, maximum VCC can be 64K connections. It can support maximum 16,384M AAL2 connections. For efficient use of peripheral memory, a concept of segment address was proposed. The proposed AAL2 switch hardware architecture can be used in ATM network as a standalone server or embedded module in a ATM switching system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.273-276
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• 1998

This paper proposes a new Asynchronous Transfer Mode(ATM) switch architecture for the Broadband ISDN. The proposed switch has the architecture to prohibit the out-of-sequence in shared buffer switch system with being fixed buffer size in the out-buffered large scale ATM Switch System. then in this paper proposes cell resequence algorithm to decrease the out-of-sequence problem. also, we studied the out-of-sequence problem that was occurred by the cell transfer delay and the cell overflow due to the fixed buffer size when cell resequenced and we propose to implement optimal ACFIFO(Address Counter First In First Out) buffer size which has the minimized cell loss.

• 한국통신학회논문지
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• 제21권1호
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• pp.131-143
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• 1996

In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.