• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.91-94
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• 2012

This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.164-166
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• 2016

PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3052-3054
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• 2005

Ubiquitous Computing 환경은 모든 사물과 공간이 지능화되어 사용자가 컴퓨터나 네트워크를 의식하지 않는 상태에서 장소에 구애받지 않고 자유롭게 네트워크에 접속할 수 있는 환경을 의미한다. 만일 이러한 환경 속에서 개인정보들이 노출되었을 경우는 법적, 사회적, 경제적으로 커다란 손실을 초래하게 된다. 이것을 방지하기 위해서는 안정성과 효율성이 높은 암호 알고리즘이 요구된다. 본 논문에서는 한국 표준으로 제정된 ISPN(Involutional SPN) 구조의 블록 암호화 ARIA 알고리즘을 사용하여 고속의 통신망과 Smart Card, PDA, 이동전화 및 다양한 기기 둥의 사용이 보편화될 Ubiquitous Computing 환경에 응용 가능한 ARIA 암호화 프로세서(이하 ARIA 프로세서)를 설계하였다.