• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2011년도 제40회 동계학술대회 초록집
• /
• pp.68-68
• /
• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• 마이크로전자및패키징학회지
• /
• 제23권1호
• /
• pp.11-15
• /
• 2016

유기발광다이오드(orgianic light emitting diodes, OLEDs)는 대형 유연 디스플레이와 발광원으로서 사물인터넷 (IoT)의 하드웨어 기기 등 다양한 분야에서 연구가 진행되고 있다. 그러나 낮은 일함수의 금속 및 쉽게 반응하는 유기재료 자체의 특성으로 인하여 외부환경에 매우 취약한 단점을 가지고 있으며 특히, 수분과 산소에 민감하여 외부와의 접촉 시 성능이 급속도로 저하되는 현상을 나타내게 된다. 이를 방지하기 위해 PVD, CVD, ALD 와 같은 방법으로 보호막 형성 연구를 진행 중에 있지만 복잡한 공정 및 높은 비용의 문제점 등이 있다. 그러므로 외부 환경에 의한 성능 저하를 차단해주는 저렴하고 단순한 공정의 페시베이션(passivation) 박막 기술 개발이 매우 중요하다. 본 연구에서는 유기발광다이오드의 수명 향상을 위하여 스핀코팅(spin-coating) 방법으로 녹색 유기발광다이오드 소자 위에 조성비에 따른 페시베이션 박막을 형성한 후 녹색 유기발광다이오드의 휘도특성 변화를 조사하였다. 페시베이션 용액은 poly vinyl alcohol (PVA)를 기반으로 sodium alginate (SA)를 0, 10, 20, 40 wt%의 조성비로 제조하였으며, 40 wt%의 조성비에서 가장 좋은 배리어 보호 특성을 나타내었다. 최종적으로 PVA + SA 용액의 최적화된 페시베이션 보호막을 제작할 수 있었다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.344-344
• /
• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 한국반도체및디스플레이장비학회:학술대회논문집
• /
• 한국반도체및디스플레이장비학회 2007년도 춘계학술대회
• /
• pp.193-198
• /
• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.180-180
• /
• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 반도체디스플레이기술학회지
• /
• 제18권1호
• /
• pp.32-37
• /
• 2019

Titanium dioxide ($TiO_2$) is a promising dielectric material in the semiconductor industry for its high dielectric constant. However, for utilization on Si substrate, $TiO_2$ film meets with a difficulty due to the large leakage currents caused by its small conduction band energy offset from Si substrate. In this study, we propose an in-situ plasma oxidation process in plasma-enhanced atomic layer deposition (PE-ALD) system to form an oxide barrier layer which can reduce the leakage currents from Si substrate to $TiO_2$ film. $TiO_2$ film depositions were followed by the plasma oxidation process using tetrakis(dimethylamino)titanium (TDMAT) as a Ti precursor. In our result, $SiO_2$ layer was successfully introduced by the plasma oxidation process and was used as a barrier layer between the Si substrate and $TiO_2$ film. Metal-oxide-semiconductor ($TiN/TiO_2/P-type$ Si substrate) capacitor with plasma oxidation barrier layer showed improved C-V and I-V characteristics compared to that without the plasma oxidation barrier layer.

• 한국전기전자재료학회논문지
• /
• 제21권1호
• /
• pp.1-4
• /
• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.267-267
• /
• 2012

$TiO_2$-Ni inverse catalysts were prepared using atomic layer deposition (ALD) process and catalytic $CO_2$ reforming of methane (CRM) reaction over catalysts (either bare Ni or $TiO_2$ coated-Ni particles) were performed using a continuous flow reactor at $800^{\circ}C$. $TiO_2$-Ni inverse catalyst showed higher catalytic reactivity at initial stage of CRM reactions at $800^{\circ}C$ comparing to bare Ni catalysts. Moreover, catalytic activity of $TiO_2$/Ni catalyst was kept high during 13 hrs of the CRM reactions at $800^{\circ}C$, whereas deactivation of bare Ni surface was started within 1hr under same conditions. The results of surface analysis using SEM, XPS, and Raman showed that deposition of graphitic carbon was effectively suppressed in a presence of $TiO_2$ nanoparticles on Ni surface, thereby improving catalytic reactivity and stability of $TiO_2$/Ni catalytic systems. We suggest that utilizing decoration effect of metal catalyst with oxide nanoaprticles is of great potential to develop metal-based catalysts with high stability and reactivity.

• 센서학회지
• /
• 제14권3호
• /
• pp.206-210
• /
• 2005

The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/$cm^{2}$-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.

• 한국재료학회지
• /
• 제17권5호
• /
• pp.263-267
• /
• 2007

Hafnium oxide $(HfO_2)$ films were deposited on Si(100) substrates by remote plasma-enhanced atomic layer deposition (PEALD) method at $250^{\circ}C$ using TEMAH [tetrakis(ethylmethylamino)hafnium] and $O_2$ plasma. $(HfO_2)$ films showed a relatively low carbon contamination of about 3 at %. As-deposited and annealed $(HfO_2)$ films showed amorphous and randomly oriented polycrystalline structure. respectively. The interfacial layer of $(HfO_2)$ films deposited using remote PEALD was Hf silicate and its thickness increased with increasing annealing temperature. The hysteresis of $(HfO_2)$ films became lower and the flat band voltages shifted towards the positive direction after annealing. Post-annealing process significantly changed the physical, chemical, and electrical properties of $(HfO_2)$ films. $(HfO_2)$ films deposited by remote PEALD using TEMAH and $O_2$ plasma showed generally improved film qualities compare to those of the films deposited by conventional ALD.