• 전력전자학회논문지
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• 제23권3호
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• pp.208-216
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• 2018

In this paper, an LLC resonant converter employing two coupled inductors on the secondary side of the converter is proposed. The conventional LLC converter exhibits serious power loss during secondary winding of the transformer because of generation of tremendous output current ripples. To overcome this problem, an LLC resonant converter with a current doubler as a rectifying circuit was recently proposed. However, the current-doubler rectifying circuit requires coupled inductors with a high coupling ratio to retain the designed resonance characteristics. Therefore, an additional hardware filter is required at the output stage to address large output current ripples. Additional design procedures are also necessary because the inductance component of the added filter affects the designed resonant network. To solve this issue, an LLC resonant converter employing two coupled inductors is proposed in this paper. Mathematical analysis shows that the proposed secondary-side current-doubler circuit does not affect the designed resonance characteristics. The operating principles and theoretical analyses are proven through a simulation and experiments with a 54 V/28 A prototype.

• 한국통신학회논문지
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• 제7권2호
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• pp.47-54
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• 1982

본 논문에서는 A/D, D/A 변환의 한 방식인 1-bit interpolation 방법을 개선, 보완한 1-bit interpolation per-channel u-law companding PCM변환방법을 제시하고 실험회로를 구성하여 이의 동작을 확인하였다. 실험회로는 시중에서 입수하기 수월한 소자들인 TTl, logic IC 및 741 OP Amp 등으로 구성하였다. 실험결과로서는 40dB에 걸친 입력 dynamic range와 40dB 이상의 출력 dynamic range를 얻을 수 있었다. 본 논문에서 제시한 per-channel A/D, D/A변환기는 현용의 공통 codec의 단점을 충분히 보완시킬 수 있을 뿐 아니라 다중화에 있어서도 상당한 잇점을 지니고 있다.

• 전자공학회논문지A
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• 제31A권3호
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1573-1576
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• 1987

A 4-bit parallel-series A/D converter has been designed using a new matrix circuit and breadboarded with transister array(TPQ2483). The simple matrix circuit is substituted for D/A converter and sebtracter-multiplier. The system has been simulated with SPICE. This converter is capable of operating at clock rate of 20MHz.

• Journal of Power Electronics
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• 제10권5호
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• pp.461-467
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• 2010

This paper proposes a new soft-switched Sepic converter. It has low switching losses and low conduction losses due to its auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of its positive and buck/boost-like DC voltage transfer function (M=D/(1-D)), the proposed converter is desirable for use in distributed power systems. The proposed converter has versions both with and without a transformer. The paper also suggests some design guidelines in terms of the power circuit and the control loop for the proposed converter.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• 한국인터넷방송통신학회논문지
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• 제8권4호
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• pp.53-58
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• 2008

본 논문은 고 해상도 및 저 전력을 가지는 시그마-델타 D/A(Digital-to-Analog) 컨버터를 구현하였다. A/D 컨버터의 출력을 채널당 1비트씩 입력 받아 LJ, RJ, I2S 모드와 비트 모드에 따라서 입력 데이터를 재구성한다. D/A 컨버터는 HBF(Half Band Filter)와 Hold, 5차 CIFB Sigma-Delta 변조기를 통과하여 원래의 아날로그 신호로 복원한다. 면적과 전력, 성능을 고려하여 곱셈 연산 대신 덧셈 연산을 반복 사용하였다. 또한, 비슷한 구조의 HBF 3개를 하나의 블록으로 구성하였고, sinc 필터 대신에 샘플-홀드 블록을 사용하여, 면적을 감소시키는 간략한 D/A 구조를 제안하였다. 블록안의 각 필터들은 매트랩 툴을 이용하여 특성을 평가하였다. 전체 블록은 Top-down 설계 방식을 사용하여, Verilog 언어로 설계하였다. 설계된 블록은 Samsung 0.35um CMOS 표준 셀 라이브러리를 사용해 칩으로 제작되었다. 칩의 면적은 1500 * 1500um 이다.

• 한국정보통신학회논문지
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• 제18권1호
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• pp.129-134
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• 2014

본 논문은 디지털-아날로그 변환기(DAC: digital-to-analog converter), SAR 로직, 그리고 비교기로 구성된 10-bit 10-MS/s 비동기 축차근사형(SAR: successive approximation register) 아날로그-디지털 변환기(ADC: analog-to-digital converter)를 제안한다. Rail-to-rail의 입력 범위를 가지는 설계된 비동기 축차근사형 아날로그-디지털 변환기는 샘플링 속도를 향상시키기 위해 MOM(metal-oxide-metal) 커패시터를 이용한 바이너리 가중치 기반의 디지털-아날로그 변환기를 사용하여 구현한다. 제안하는 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기는 0.18-${\mu}m$ CMOS 공정에서 제작되고 면적은 $0.103mm^2$를 차지한다. 1.1 V의 공급전압에서 전력소모는 0.37 mW를 나타낸다. 101.12 kHz와 5.12 MHz의 아날로그 입력 신호에 대해 측정된 SNDR은 각각 54.19 dB와 51.59 dB이다.