• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.37-43
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• 2007

In this.paper, we introduce design and implementation results of the single balanced diode mixer for European point-to-point microwave radio in order to improve flatness performance. When a resonator such as RF filter is integrated with a mixer, impedance characteristic of 50 ohm is maintained only in RF band, not in LO band resulting deterioration of flatness performance because of LO power variation on the diode. In the paper, we suggest a design method of mixer integrated with image rejection filter and LO harmonic filter to have a better performance of flatness using embedding electrical length between filter and mixer's port. Frequency specification of fabricated mixer is $21.2{\sim}22.6\;GHz$ for RF, $19.32{\sim}20.72\;GHz$ for LO and 1.88 GHz+/-50 MHz for IF, respectively. Measured results show conversion loss of 8.5 dB, flatness of 2 dB, input PldB of 8 dBm, IIP3 of 15 dBm under LO power level of 10 dBm. Return losses of RF, LO and IF port are under -12 dB, -10 dB and -5 dB, respectively. Isolations of LO/RF and LO/IF are 20 dB and 50 dB, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.159-165
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• 2018

In this paper, a low-loss wideband waveguide transducer is proposed for millimeter-wave communication and radar applications. A conventional E-plane probe transducer is generally designed using thin and flexible substrate at millimeter-wave frequencies, considering the very small waveguide size. However, it results in serious performance degradation caused by the bending of the substrate. In order to alleviate this problem and provide a reliable performance, we propose an extended E-plane probe transducer where the probe substrate is extended to and fix ed in the slit area formed in the waveguide wall. It is fabricated using $127{\mu}m$-thick substrate with dielectric constant of 2.2. The measurement in the back-to-hack configuration shows the excellent insertion loss of 1.35 dB (${\pm}0.35dB$) including the loss of 3 cm-long thru waveguide and return loss better than 13.8 dB over entire W-band (75-110 GHz). Therefore, it can be effectively applied for millimeter-wave high-speed communications and high-sensitivity radars.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.31-37
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• 1998

Magnitude/phase controlling circuit which is composed of attenuator and phase shifter make phase/gain cross-coupling, so too much tuning time is needed to find optimum operation point. In this paper, vector attenuator which control magnitude and phase of input signals is proposed. Vector attenuator in past ignores phase variation characteristics of attenuator, but vector attenuator of this paper compensates phase variation characteristics of attenuator. This vector attenuator consists of 0$^{\circ}$/180$^{\circ}$ phase shifter and low phase shifting attenuator and so forth. A 0$^{\circ}$/180$^{\circ}$ phase shifter has 0$^{\circ}$/179.9$^{\circ}$ phase shifting characteristics at a center frequency 881 MHz and a low phase shifting attenuator has an attenuation of 25dB, within the limit of 3.6$^{\circ}$ phase shift and less than -20dB reflection characteristics at both input and output ports. The designed vector attenuator shows that cartesian coordinate plane of output signal space can be represented correctly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.62-68
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• 2000

It was designed a high-speed analog input card that is a important device of ultrasonic testing flaw detector in the middle of non-destructive testing in this Paper. The A/D Board is inquired high-speed sampling rate and fast data acquisition system. This pater shows a design that has a function of Peak- Detection for ultrasonic testing by ISA Bus type and a 50MHz of A/D converter in order to do sampling more than quadruple frequency of transducer frequency.

• The KIPS Transactions:PartD
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• v.18D no.6
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• pp.443-450
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• 2011

Model-based Component development methodologies consider the whole system as an component and develop physical components through recursive decomposition and refinements of components in a top-down manner. We developed a model translator that can be used to formally verify interaction consistency among components, especially the interaction behavior between before- and after- refinements of components. This translator can be used to identify potential problems in the refinement process so that problems can be addressed from the early stage of development. This paper introduces our translation approach and the organization of the translator. The translator has been applied to two case studies to show its usefulness.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.