• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.753-757
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• 2011

The possibility of implementing nonuniform residual dispersion per span (RDPS) in optical links with net residual dispersion (NRD) controlled by precompensation and postcompensation for 960 Gbps WDM transmissions is studied and discussed. The fiber optic communication links investigated in this paper consist of inline dispersion management (DM) for each fiber spans and optical phase conjugator (OPC) at mid-way of total transmission length in order to compensate for WDM signal distortions due to group velocity dispersion (GVD) and nonlinearities. It is confirmed that the effect of nonuniform RDPS distribution on system performance is not significant. It is also confirmed that the optimal NRD is obtained to be one of two values of +10 ps/nm or -10 ps/nm, which depend on the deciding of NRD controlled by precompensation or postcompensation, and the exact RDPS configurations. The effective NRD ranges resulting eye opening penalty (EOP) below 1 dB are independent on the exact RDPS distribution for relative low launch power. Therefore, results show the possibility of implementing the flexible optical links to expand network construction for WDM transmission of high bit-rate capability.

• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• International journal of advanced smart convergence
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• v.9 no.2
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• pp.68-75
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• 2020

Non-orthogonal multiple access (NOMA) has gained the significant attention in the fifth generation (5G) mobile communication, which enables the advanced smart convergence of the artificial intelligence (AI), the internet of things (IoT), and many of the state-of-the-art technologies. Recently, correlated superposition coding (SC) has been proposed in NOMA, to achieve the near-perfect successive interference cancellation (SIC) bit-error rate (BER) performance for the stronger channel users, and to mitigate the severe BER performance degradation for the weaker channel users. In the correlated SC NOMA scheme, the stronger channel user BER performance is even better than the perfect SIC BER performance, for some range of the power allocation factor. However, such excessively good BER performance is not good for the user-fairness, i.e., the more power to the weaker channel user and the less power to the stronger channel user, because the excessively good BER performance of the stronger channel user results in the worse BER performance of the weaker channel user. Therefore, in this paper, we propose the power splitting to establish the user-fairness between both users. First, we derive a closed-form expression for the power splitting factor. Then it is shown that in terms of BER performance, the user-fairness is established between the two users. In result, the power splitting scheme could be considered in correlated SC NOMA for the user-fairness.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.23-26
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• 2000

본 논문에서는 국제 통신 표준화기구인 ITU-T에서 인터넷폰과 화상회의를 목적으로 채택된 G.723.1 음성 부호화 시스템을 TMS320C5409를 이용하여 전 과정을 어셈블리어로 실시간 구현하였다. 구현된 G.723.1 음성 부호화기는 6.3kbps 전송률일 때 인코더 25.75MIPS이고 디코더 1.99MIPS의 최대 복잡도를 나타내고, 5.3kbps 전송률일 때 인코더 17.69MIPS이고 디코더 1.9Ml PS의 최대 복잡도를 나타낸다. 사용된 메모리는 program ROM llkwords, data ROM(table) 9.45kwords, RAM 2.8kwords 정도이며, 실시간 처리된 출력음성은 C simulation결과와 같은 음질을 보였다. 구현된 G.723.1 음성 부호화기는 ITU-T에서 제공되는17개의 테스트 벡터를 모두bit-exact하게 통과하였다.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.5
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• pp.107-112
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• 2020

Ultra-lightweight password CHAM is an algorithm with efficient addition, rotation and XOR operations on resource constrained devices. CHAM shows high computational performance, especially on IoT platforms. However, lightweight block encryption algorithms used on the Internet of Things may be vulnerable to side channel analysis. In this paper, we demonstrate the vulnerability to side channel attack by attempting a first power analysis attack against CHAM. In addition, a safe algorithm was proposed and implemented by applying a masking technique to safely defend the attack. This implementation implements an efficient and secure CHAM block cipher using the instruction set of an 8-bit AVR processor.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.9
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• pp.237-246
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• 2016

DIBR (Depth Image Based Rendering) is a multimedia technology that generates the virtual multi-view images using a color image and a depth image, and it is used for creating glasses-less 3-dimensional display contents. This research describes the effect of depth accuracy about the objective quality of DIBR-based multi-view images. It first evaluated the minimum depth quantization bit that enables the minimum distortion so that people cannot recognize the quality degradation. It then presented the comparative analysis of non-uniform domain-division quantization versus regular linear quantization to find out how effectively express the accuracy of the depth information in same quantization levels according to scene properties.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.1
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• pp.67-74
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• 2008

As wireless network market is increasing rapidly, the biggest issue is to transfer safe data and to authenticate users. This paper proposes ECbA(Elliptic Curve based Authentication) which consists of the mutual authentication mechanism that users can ascertain the identity of an authentication server and the user authentication mechanism that an authentication server can make sure users' identity, by using Elliptic Curve algorithms. The proposed ECbA system diminishes the message quantity and the execution time by using the small elliptic curve algorithm with the small key length in authentication. In addition, as this paper reduces the authentication steps of existing EAP_TLS into 6 authentication steps, the communication cost and mutual authentication time can be saved. As this paper distributes new keys, whenever authenticating users by using key exchange mechanism, it provides safe encryption communication and prevents DoS attack by controlling the users authentication request by authentication server.