• Title/Summary/Keyword: 9 bit 통신

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A Study on ${\pi}$/4-DQPSK with Nonredundant Multiple Error Correction

  • Song, Seog-Il;Han, Young-Yearl
    • ETRI Journal
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    • v.21 no.2
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    • pp.9-21
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    • 1999
  • In this paper, to enhance the performance of ${\pi}$/4-DQPSK (${\pi}$/4-differential quadrature phase shift keying), the scheme using nonredundant multiple error correction is proposed and investigated. This scheme for the differential detection of ${\pi}$/4-DQPSK uses the signal output which is delayed for more than two time slots as the parity check bit and applies it to nonredundant multiple error correction. The proposed system was used for studying the performance of ${\pi}$/4-DQPSK with Nonredundant Error Correction (NEC) in additive white Gaussian noise (AWGN) and Nakagami fade modeled mobile communication channel, and it was observed that the performance increased as the error correction capability increased.

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An Extension of Firmware-based LFSR One-Time Password Generators

  • HoonJae Lee;ByungGook Lee
    • International journal of advanced smart convergence
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    • v.13 no.2
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    • pp.35-43
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    • 2024
  • In this paper, we propose two 127-bit LFSR (Linear Feedback Shift Register)-based OTP (One-Time Password) generators. One is a 9-digit decimal OTP generator with thirty taps, while the other is a 12-digit OTP generator with forty taps. The 9-digit OTP generator includes only the positions of Fibonacci numbers to enhance randomness, whereas the 12-digit OTP generator includes the positions of prime numbers and odd numbers. Both proposed OTP generators are implemented on an Arduino module, and randomness evaluations indicate that the generators perform well across six criteria and are straightforward to implement with Arduino.

Modified Gaussian Approximation for Multiple Access Interference of UWB-TH system with BPSK (UWB-TH BPSK 시스템의 다중 사용자 간섭을 위한 개선된 가우시안 근사)

  • Park, Jang-Woo;Cho, Sung-Eon;Cho, Kyung-Ryung
    • Journal of Advanced Navigation Technology
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    • v.9 no.1
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    • pp.56-60
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    • 2005
  • To calculate the probability of bit error of UWB communication systems, the exact expression of multiple access interference is essential. So far, in many researches, MAI has been modeled by the Gaussian Approximation, which leads to the huge errors. And there are some tries to obtain the exact model fot the MAI but they have some problems such as long calculation time. We introduce the simple expression to calculate the probability of error of an UWB-TH system with BPSK. The multiple access interference is explained by the characteristic function method combined with the Gaussian approximation. It allows us to easily and fast calculate the bit error rate of an UWB-TH system.

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A Bit Rate Control of MPEG-4 AVC Video Coding Using Adaptive Quantization (적응 양자화를 이용한 MPEG-4 AVC의 비디오 율 제어 방법)

  • 유충열;신규철;박재두;이명호
    • Journal of Broadcast Engineering
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    • v.9 no.2
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    • pp.142-150
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    • 2004
  • MPEG-4 AVC is an international video coding standard that is being developed. The standardization is mainly targeted at a very high compression ratio. MPEG-4 AVC is a general video coding technology that may be used in various applications. Therefore, MPEG-4 AVC needs an efficient rate control method to be applied in various communication environments. This paper is based on the rate control method that considers human visual characteristic. In this paper, we propose the constant bit rate control method using adaptive quantization and scene change detection. Experiments performed using various test images and experimentation results exhibits a favorable performance over existing rate control methods.

Development of Peripheral Units of the 16 bit Micro-Controller for Mobile Telecommunication Terminal (이동통신 단말기용 16 비트 마이크로콘트롤러의 주변장치 개발)

  • 박성모;이남길;김형길;김세균
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.9
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    • pp.142-151
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    • 1995
  • The trend of compact size, light weight, low power consumption in the portable telecommunication equipments demands large scale integration and low voltage operation of chips and the minimization of the number of the components in the telecommunication terminal. According to the trend, existing chip components are modulized and are integrated as a part into a bigger chip. This paper is about the development of the peripheral units of micro-controller for mobile telecommunication terminal. Peripherals consist of DMA controller, Interrupt controller, timer, watchdog timer, clock generator, and power management unit. They are designed to be integrated with EU(Execution Unit) and BIU(Bus Interface Unit) into a 16 bit micro-controller which will be used as a core of an ASIC for next generation digital mobile telecommunication terminal. At first, whole block of the micro-controller was described by VHDL behavioral model and simulated to verify its overall operation. Then, watchdog timer, clock generator and power management unit were directly synthesized by using VHDL synthesis tool. Rest of the pheriperal units were designed and simulated by using Compass Design Tool.

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Lightpaths Routing for Single Link Failure Survivability in IP-over-WDM Networks

  • Javed, Muhammad;Thulasiraman, Krishnaiyan;Xue, Guoliang(Larry)
    • Journal of Communications and Networks
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    • v.9 no.4
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    • pp.394-401
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    • 2007
  • High speed all optical network is a viable option to satisfy the exponential growth of internet usage in the recent years. Optical networks offer very high bit rates and, by employing technologies like internet protocol over wavelength division multiplexing(IP-over-WDM), these high bit rates can be effectively utilized. However, failure of a network component, carrying such high speed data traffic can result in enormous loss of data in a few seconds and persistence of a failure can severely degrade the performance of the entire network. Designing IP-over-WDM networks, which can withstand failures, has been subject of considerable interest in the research community recently. Most of the research is focused on the failure of optical links in the network. This paper addresses the problem of designing IP-over-WDM networks that do not suffer service degradation in case of a single link failure. The paper proposes an approach based on the framework provided by a recent paper by M. Kurant and P. Thiran. The proposed approach can be used to design large survivable IP-over-WDM networks.

Performance and Energy Consumption Analysis of 802.11 with FEC Codes over Wireless Sensor Networks

  • Ahn, Jong-Suk;Yoon, Jong-Hyuk;Lee, Kang-Woo
    • Journal of Communications and Networks
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    • v.9 no.3
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    • pp.265-273
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    • 2007
  • This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

FPGA Implementation of Elliptic Curve Cryptography Processor as Intellectual Property (타원곡선 암호연산 IP의 FPGA구현)

  • Moon, San-Gook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.670-673
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    • 2008
  • Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

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Weight-based Congestion Control Algorithms for H.264/SVC Streaming (H.264/SVC 스트리밍을 위한 가중치 기반 혼잡 제어 알고리즘)

  • Kim, Nam-Yun
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.2
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    • pp.9-17
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    • 2012
  • Because best-effort Internet provides no guarantees on packet delay and loss, transient network congestion may cause negative effects on H.264/SVC streaming. Thus, the congestion control is required to adjust bit rate by dropping enhancement layers of H.264/SVC streams. This paper differentiates the video streams according to different levels of importance and proposes weighted-based congestion control algorithms to use the rate-distortion characteristics of streams. To maximize the weighted sum of PSNR values of all streams on a bandwidth-constrained node, this paper proposes WNS(Weighted Near-Sighted) and WFS(Weighted Far-Sighted) algorithms to control the number of enhancement layers of streams. Through simulation, this paper shows that weighted-based congestion control algorithm can efficiently adapt streams to network conditions and analyzes the characteristics of congestion control algorithms.

A Design of High-speed Phase Calculator for 3D Depth Image Extraction from TOF Sensor Data (TOF 센서용 3차원 Depth Image 추출을 위한 고속 위상 연산기 설계)

  • Koo, Jung-Youn;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.355-362
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    • 2013
  • A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.