• Transactions of the Korean hydrogen and new energy society
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• v.29 no.5
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• pp.434-441
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• 2018

The pore size of nickel (Ni) bottom electrode layer (BEL) for low-temperature solid oxide fuel cells embedded with ultrathin-film electrolyte was controlled by changing the substrate surface morphology and deposition process parameters. For ~150-nm-thick Ni BEL, the upper side of an anodic aluminum oxide (AAO) substrate with ~65-nm-sized pores provided ~1.7 times smaller pore size than the lower side of the AAO substrate. For ~100-nm-thick Ni BEL, the AAO substrate with ~45-nm-sized pores provided ~2.6 times smaller pore size than the AAO substrate with ~95-nm-sized pores, and the deposition pressure of ~4 mTorr provided ~1.3 times smaller pore size than that of ~48 mTorr. On the AAO substrate with ~65-nm-sized pores, the Ni BEL deposited for 400 seconds had ~2 times smaller pore size than the Ni BEL deposited for 100 seconds.

• ETRI Journal
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• v.32 no.3
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• pp.457-459
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• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• Journal of the Korean Ceramic Society
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• v.41 no.7
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• pp.528-533
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• 2004

Macroporous SiC with pore size 84∼658 nm and mesoporous SiC with pore size 15∼65 nm were respectively prepared by infiltrating low viscosity preceramic polymer solutions into the various sacrificial templates obtained by natural sedimentation or centrifuge of 20∼700 nm silica sol, which were subsequently etched off with HF after pyrolysis at 1000∼140$0^{\circ}C$ in an argon atmosphere. Three-dimensionally long range ordered macroporous SiC ceramics derived from polymethylsilane (PMS) showed surface area 584.64$m^2$g$^{-1}$ when prepared with 112nm silica sol and at 140$0^{\circ}C$, whereas mesoporous SiC from polycarbosilane (PCS) exhibited the highest surface area 619.4 $m^2$g$^{-1}$ with random pore array when prepared with 20-30 nm silica sol and at 100$0^{\circ}C$. Finally, tile pore characteristics of porous SiC on the types of silica sol, polymers and pyrolytic conditions were interpreted with the analytical results of SEM, TEM, and BET instruments.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.65-65
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• 2004

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.6
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• pp.60-65
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• 2002

The purpose of this study is to measure and compare the output power characteristics and optical gain for selenium vapour laser depending on the He gas purity. The purity of the He gas was improved with a special He-filter. During the measurement the individual wavelengths were selected with a birefringent filter. The result shows that compared with those of laser without He-filter, the output-coupling power and small signal gain of laser with He-filter increase in the most of the lines. Especially, the output-coupling power and small signal gain for the strong lines (497.6 nm, 499.3 nm, 506.9 nm, 517.6 nm, 522.8 nm, 530.5 nm), blue(460.4 nm, 464.8 nm) and red(644.4 nm 649.1 nm) lines lies notably higher.

• Journal of the Korean Magnetics Society
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• v.15 no.2
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• pp.61-66
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• 2005

In order to make submicron cell for spin-injection device, lift-off method using Pt stencil and wet etching was chosen. This approach allows batch fabrication of stencil substrate with electron-beam lithography. It simplifies the process between magnetic film stack deposition and final device testing, thus enabling rapid turnaround in sample fabrication. Submicron junctions with size of $200nm{\times}300nm$ and $500nm{\times}500nm$ 500 nm and pseudo spin valve structure of $CoFe(30{\AA})/Cu(100{\AA})/CoFe(120{\AA}$) was deposited into the nanojunctions. MR ratio was 0.8 and $1.1{\%}$, respectively and spin transfer effect was confirmed with critical current of $7.65{\times}10^7A/cm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.330-333
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• 2016

In this paper, we propose 77 GHz power amplifier for long range automotive collision avoidance radar using 65 nm CMOS process. The proposed circuit has a 3-stage single power amplifier which includes common source structure and transformer. The measurement results show 18.7 dB maximum voltage gain at 13 GHz 3 dB bandwidth. The measured maximum output power is 10.2 dBm, input $P_{1dB}$ is -12 dBm, output $P_{1dB}$ is 5.7 dBm, and maximum power add efficiency is 7.2 %. The power amplifier consumes 140.4 mW DC power from 1.2 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.403-409
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• 2013

In this work, a CMOS two stage differential power amplifier which includes Marchand balun, transformer and injection-locked buffer is presented. The power amplifier is targeted for 70 GHz frequency band and fabricated using 65 nm technology. The measurement results show 8.5 dB maximum voltage gain at 71.3 GHz and 7.3 GHz 3 dB bandwidth. The measured maximum output power is 8.2 dBm, input $P_{1dB}$ is -2.8 dBm, output $P_{1dB}$ is 4.6 dBm and maximum power added efficiency is 4.9 %. The power amplifier consumes 102 mW DC power from 1.2 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.7
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• pp.791-794
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• 2014

In this work, a 300 GHz imaging detector has been developed and image has been acquired in a 65-nm CMOS technology. The circuit was designed based on the square-law of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 2,270 V/W and minimum NEP of $38pW/Hz^{1/2}$ at 285 GHz, and NEP< ${\sim}200pW/Hz^{1/2}$ for 250~305 GHz range. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.