• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.349-352
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• 2000

In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35$\mu\textrm{m}$ standard cell library. The synthesis result shows that this MAC unit can operate at 80㎒ of clock frequency in 85$^{\circ}C$, 3.0V, worst case process and 125㎒ of clock frequency at 25$^{\circ}C$, 3.3V, typical case process. It achieves 320Mops of performance, and is suitable for embedded DSP processors.

• Proceedings of the Optical Society of Korea Conference
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• 1998.08a
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• pp.98-99
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• 1998

In this paper, an acousto-optic defiector9ADO) is used to perform the angular multiplexing without moving parts. The error-correction coding techniques was used to achive low bit-error rates in the experiment. A part of Lena image(64*64) encoded by Reed-Solomon codes were stored and retrieved.

• Food Science and Industry
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• v.43 no.1
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• pp.64-69
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• 2010

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2081-2093
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• 1994

In this study, we design and implement 64 QAM demodulator which has 155 Mbps, first level of CCITT G707 SDH(Synchronous Digital Hierachy) for STM 1 signal transmission. Carrier recovery which effects the demodulator performance uses decision feedback carrier using 8 bits A/D converter. Also, PSF(Pulse Shaping Filter) is 7 order elliptic filter. Carrier recovery circuit is designed and implemented digital type which use high 3 bits of 8 bits conversion data as data and the order low bits as error data and hybrid type which use VCO and analog integrator. Therefore we obtain stable performance recovery.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1128-1135
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• 2001

In this paper, a new HSG-Si formation technology, "seeding method', which employs Si$_2$H$_{6}$-molecule irradiation and annealing, was applied for realizing 64Mbit DRAMs. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous-doped amorphous-Si electrode. The new HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors. In this technique, optimum process conditions of the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 400$\AA$, respectively. In the 64M bit DRAM capacitor using optimum process conditions, limit thickness of dielectric nitride is about 65$\AA$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.1
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• pp.33-41
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• 2012

A differential fault analysis(DFA) is one of the most important side channel attacks on block ciphers. Most block ciphers, such as DES, AES, ARIA, SEED and so on., have been analysed by this attack. PRESENT is a 64-bit block cipher with 80/128-bit secret keys and has a 31-round SP-network. So far, several DFAs on PRESENT have been proposed. These attacks recovered 80, 128-bit secret keys of PRESENT with 8~64 fault injections. respectively. In this paper, we propose an improved DFA on PRESENT-80/128. Our attack can reduce the complexity of exhaustive search of PRESENT-80(resp. 128) to on average 1.7(resp. $2^{22.3}$) with 2(resp. 3) fault injections, From these results, our attack results are superior to known DFAs on PRESENT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.731-742
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• 2022

PIPO is the latest domestic lightweight block cipher announced in ICISC'20, which is characterized by being lightweight to facilitate implementation on IoT with limited resources. In this paper, PIPO 64/128-bit and 64/256-bit were implemented using web-based languages such as Javascript and WebAsembly. Two methods of performance evaluation were conducted by implementing bitsice and TLU, and the performance was compared by implementing Looped written using for statements and Unrolled written for statements. It performs performance evaluations in various web browsers such as Google Chrome, Mozilla Firefox, Opera, and Microsoft Edge, as well as OS-specific environments such as Windows, Linux, Mac, iOS, and Android. In addition, a performance comparison was performed with PIPO implemented in C language. This can be used as an indicator for applying PIPO block cipher on the web.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.163-166
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• 2021

ICISC'20에서 발표된 경량 블록암호 PIPO는 비트 슬라이스 기법 적용으로 효율적인 구현이 되었으며, 부채널 내성을 지니기에 안전하지 않은 환경에서도 안정적으로 사용 가능한 경량 블록암호이다. 본 논문에서는 ARM 프로세서를 대상으로 PIPO의 병렬 최적 구현을 제안한다. 제안하는 구현물은 8평문, 16평문의 병렬 암호화가 가능하다. 구현에는 최적의 명령어 활용, 레지스터 내부 정렬, 로테이션 연산 최적화 기법을 사용하였다. 구현은 A10x fusion 프로세서를 대상으로 한다. 대상 프로세서상에서, 기존 레퍼런스 PIPO 코드는 64/128, 64/256 규격에서 각각 34.6 cpb, 44.7 cpb의 성능을 가지나, 제안하는 기법은 8평문 64/128, 64/256 규격에서 각각 12.0 cpb, 15.6 cpb, 16평문 64/128, 64/256 규격에서 각각 6.3 cpb, 8.1 cpb의 성능을 보여준다. 이는 기존 대비 각 규격별로 8평문 병렬 구현물은 약 65.3%, 66.4%, 16평문 병렬 구현물은 약 81.8%, 82.1% 더 좋은 성능을 보인다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.176-178
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• 1988

In this paper, techniques of constructing parity check matrix of SBEC-DBED codes will be presented to improve reliability of muliti-bit-per-chip type memory systems. And the high speed parallel CODEC of (88.64)SBEC-DBED code which is applicable to real system will be designed.