• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.668-675
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• 2002

This paper proposes pre-distorter combined LUT with 2ιpartition interpolation method to reduce nonlinear distortion which was caused by high PAPR and to update LUT quickly. Pre-distorted gain and phase can be found by using LUT which consisted of AM/AM and AM/PM value, and OFDM signal amplitude. The proposed 2ιpartition interpolation can accurately find predistorted gain and phase using bit shift and add component instead of increasing size of LUT which requires increasing the amount of computation. The performance of the proposed method was measured by the difference between HPA input and output characteristics by the LUT size, constellation, SER performance by the HPA, and LUT update error by the HPA characteristic changes. As a result, it is shown that when the size of the LUT is 32 and 64 for 16-QAM and 64-QAM, nonlinear distortion nearly didn't occurred.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.31-39
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• 2011

In this paper, we propose a signal readout system with small area and low power consumption for CNT sensor arrays. The proposed system consists of signal readout circuitry, a digital controller, and UART I/O. The key components of the signal readout circuitry are 64 transimpedance amplifiers (TIA) and SAR-ADC with 11-bit resolution. The TIA adopts an active input current mirror (AICM) for voltage biasing and current amplification of a sensor. The proposed architecture can reduce area and power without sampling rate degradation because the 64 TIAs share a variable gain amplifier (VGA) which needs large area and high power due to resistive feedback. In addition, the SAR-ADC is designed for low power with modified algorithm where the operation of the lower bits can be skipped according to an input voltage level. The operation of ADC is controlled by a digital controller based on UART protocol. The data of ADC can be monitored on a computer terminal. The signal readout circuitry was designed with 0.13${\mu}m$ CMOS technology. It occupies the area of 0.173 $mm^2$ and consumes 77.06${\mu}W$ at the conversion rate of 640 samples/s. According to measurement, the linearity error is under 5.3% in the input sensing current range of 10nA - 10${\mu}A$. The UART I/O and the digital controller were designed with 0.18${\mu}m$ CMOS technology and their area is 0.251 $mm^2$.

• The Journal of the Acoustical Society of Korea
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• v.14 no.1
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• pp.40-47
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• 1995

Due to rapid progress in data communications, we are able to acquire the information we need with ease. One means of achieving this is a parallel machine such as the MasPar. Although the parallel machine makes it possible to receive/transmit enormous quantities of data, because of the increasing volume of information that must be processed, it is necessary to transmit only a minimal amount of data bits. This paper suggests a new coding method for the parallel machine, which compresses the data by reducing redundancy. Parallel Dynamic Octal Compact Mapping (PDOCM) compresses at least 1 byte per word, compared with other coding techniques, and achieves a 54.188-fold speedup with 64 processors to transmit 10 million characters.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.

• Journal of Advanced Navigation Technology
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• v.16 no.5
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• pp.871-878
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• 2012

LBlock is a 64-bit ultra-light block cipher suitable for the constrained environments such as wireless sensor network environments. In this paper, we propose a differential fault analysis on LBlock. Based on a random nibble fault model, our attack can recover the secret key of LBlock by using the exhaustive search of $2^{25}$ and five random nibble fault injection on average. It can be simulated on a general PC within a few seconds. This result is superior to known differential fault analytic result on LBlock.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.120-126
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• 2005

This paper presents the 3D wavelet based video compression system using quad-tree algorithm. The 3D wavelet based video compression system removes the temporal correlation of the input sequences using the motion compensation filter and decomposes the spatio-temporal subband using the spatial wavelet transform. The proposed system allocates the higher bit rate to the low frequency image of the 3D wavelet sequences and improves the 0.64dB PSNR performance of the reconstructed image in comparison with that of H.263. In addition to the limitation on the propagation of the motion compensation error by the 3D wavelet transform, the proposed system progressively transmits the input sequence according to the resolution and rate scalability.

• ETRI Journal
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• v.37 no.6
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1612-1620
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• 2003

This papers describes a nonlinear transfer function modelling of designed GaAs FET power amplifier by measured and simulated values of designed PA amplifier for multi­carrier transmission system, With the results of PA nonlinearity characteristic, we can estimates AM­AM and AM­PM of designed PA. According to the estimated nonlinear characteristics, we can analysis the ACPR of PA for spectral regrowth, the error vector measurement(EVM) of constallation signals and bit error rate of QPSK and 64­QAM. The suggested nonlinear modelling results are used to get an accurate estimate of digital characteristics between PA amplifier and wireless multi­carrier transmission system using OFDM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.257-269
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• 2003

S(Synchrous)-DMT(Discrete Multi Tone) is an emerging cable modem technology applicable to the upstream channel for high speed multimedia communication. In this paper we analyze the transmitting and receiving process of S-DMT scheme and derive bit error probability of S-DMT scheme in the $\varepsilon$-mixture impulse noise model which appropriately reflects impulse noise model which approproately reflects impulse noise characteristics of upstream channel. The analysis results show a good match with the simulation results. We also compare Eb/No gain performance of S-DMT with TDMA in 16-, 32-, 64-QAM.