• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.603-609
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• 2008

Slotless linear brushless DC motor are widely used in precision machine applications because of their advantages such as low of detent force, negligible iron loss. But they have a disadvantage such as low thrust density, thrust ripple, and excessive use of permanent magnet materials. These lead to undesirable performance and high production cost. In this paper, we deal with the design and characteristics investigation of a air-core tubular linear brushless DC(TLBLDC) motor with air-core stator and permanent magnet mover. And to investigate the static and dynamic characteristics of air-core TLBLDC motor, the prototype machine is manufactured and analyzed by F.E.M. and Matlab simulink simulations. Especially, dynamic characteristics of air-core TLBLDC motor driven with 6 step inverter are simulated by F.E.M.coupling with external circuit and Matlab simulink program, and measured for the prototype motor. The simulation results are compared to the experimental results such as current waves, thrust and speed curve.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.80-82
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• 2005

This paper presents the dynamic characteristics of a linear brushless DC(BLDC) motor with permanent magnet excitation for the precision conveyor according to the load condition. In order to investigate the accurate dynamic performance of tile linear BLDC motor driving with 6 step inverter- fed, finite element techniques coupling with external circuit models, together with the simultaneous simulation of motion of the mover system, arc proposed. The results of finite element analysis arc compared to the experimental ones.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.533-541
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• 2011

This paper studies modeling of Jeju 80kV HVDC system and its controller by using PSCAD/EMTDC program. Reduced ac network is applied to verify interaction between ac network and dc system. Design parameter is applied to the converter transformer, harmonic filter and dc transmisstion line to simulate dc system. HVDC controller is divided into a rectifier controller and a inverter controller according to the converter operating mode. The inverter controller is composed of current control, voltage control and extingtion angle control. The rectifier controller is composed of current control and voltage control. Both controller has VDCOL characteristics so that current order is dependant on voltage variation. Step response, ac network single phase fault, three phase fault is simulated to verify the dynamic performance of controller model in both transient state and steady state.

• Journal of Power Electronics
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• v.15 no.3
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• pp.712-720
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• 2015

A model predictive current control (MPCC) method that does not employ a cost function is proposed. The MPCC method can decrease common-mode voltages in loads fed by three-phase voltage-source inverters. Only non-zero-voltage vectors are considered as finite control elements to regulate load currents and decrease common-mode voltages. Furthermore, the three-phase future reference voltage vector is calculated on the basis of an inverse dynamics model, and the location of the one-step future voltage vector is determined at every sampling period. Given this location, a non-zero optimal future voltage vector is directly determined without repeatedly calculating the cost values obtained by each voltage vector through a cost function. Without utilizing the zero-voltage vectors, the proposed MPCC method can restrict the common-mode voltage within ± V_dc/6, whereas the common-mode voltages of the conventional MPCC method vary within ± V_dc/2. The performance of the proposed method with the reduced common-mode voltage and no cost function is evaluated in terms of the total harmonic distortions and current errors of the load currents. Simulation and experimental results are presented to verify the effectiveness of the proposed method operated without a cost function, which can reduce the common-mode voltage.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.10
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• pp.186-192
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• 1998

This paper presents a high performance low switching PWM technique or the propulsion system of railway such as subway and high speed train. In order to achieve the continuous voltage control to six-step and s low harmonics with low switching frequency under 500Hz, the synchronous technique is combined with a space vector overmodulation and implemented by using DSP. Improved performance and a validation of proposed method are showed by the digital simulation and the experimental results using a 1.65MVA IGBT VVVF inverter and inertia load equivalent to 160 tons railway cars.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.1
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• pp.26-35
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• 1986

In this paper, non-linear state equations for a 3-phase, 220V, 0.4 KW, squirrel cage induction motor have been derived using the d-q transformation and then these equations have been linearized around an operating point by a small perturbation method. Root loci on the s-plane with repect to the changes of slip S and supply frequency f have been studied. Based on the above results, the derived linear state equations have been augmented to the 6th order, including the output velocity feedback and a discrete PI speed controller. Using the new state equations, stability regions on the Kp-Kl plane have been investigated for slip S and sampling time T. In designing a discrete PI controller, the coefficients Kp and Kl around the normal operating point (220V,1,692rpm,60Hz)have been chosen under the assumptions that each response to a perturbation input of reference speed and load torque be underdamped and dominated by a pair of complex poles. Step responses in the experimental system using an Intel SDK-86 and an optimized PWM inverter show satisfactory results that the maximum overshoots and damped frequency are well coincided with ones from the computer simulation.

• ETRI Journal
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• v.36 no.6
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• pp.905-912
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• 2014

In this paper, a new architecture is proposed to achieve complexity efficiency in implementing variable pulse position modulation (VPPM). VPPM, specified in IEEE 802.15.7, can support wireless communication and dimming control simultaneously using visible light. The proposed architecture is based on the VPPM signal property in which the transition point of the modulated output is obtained by counting the sample index and comparing it to both the assigned dimming factor and the transmitting data. Therefore, the proposed architecture can be composed of simple logics, including a counter, a comparator, and an inverter, all of which are insensitive to the dimming resolution in contrast to a conventional codeword-table method. This paper describes the verification of the proposed algorithm through a register-transfer level implementation of the codeword and proposed architectures. In comparison with the codeword-table method, the proposed method gains a nine-fold complexity reduction at a 1% dimming-step resolution.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.6
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• pp.117-125
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• 2007

Recently, a fuel cell with low voltage and high current output characteristics is remarkable for new generation system. It needs both a DC-DC step-up converter and DC-AC inverter to be used in fuel cell generation system. Therefor, this paper, consists of an isolated DC-DC converter to boost the fuel cell voltage 380[VDC] and a PWM inverter with LC filter to convent the DC voltage to single-phase 220[VAC]. Expressly, The fuel cell system which it proposes DC-DC the efficient converter used PWM the phase transient control law and it depended to portion resonance ZVS switching, loss peek voltage and electric current of realization under make schedule, switching frequency anger and the switch reduction. And mind benevolence it sprouted 2 in stop circuit and it added and a direct current voltage and the electric current where the ingredient is reduced in load side ripple stable under make whom it will be able to supply. Besides the efficiency of 92[%]is obtained over the wide output voltage regulation ranges and load variations. Also, under make over together the result leads simulation and test, the propriety confirmation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1052-1058
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• 2005

This paper dealt with the design and fabrication of a low frequency electronic ballast for ruh attracting lamps. The proposed electronic ballast was composed of a full-wave rectifier, a step don converter operated as a constant power controled current source, an inverter operated by 130 Hz square wave, and an ignition circuit. An acoustic resonance phenomenon of discharge lamps could be eliminated by application of 130 Hz square wave. Also, a circuit of high voltage pulse generation for lamp ignition was added to the ballast. From the experimental results, voltage and current of the lamp operated by the electronic ballast were estimated 132.5 V and 7.6 A, respectively. and the power consumption was about 1,000 W. The weight of the ballast, which is one of important advantages, was reduced to one-fifth of conventional magnetic ballasts.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.