• Korean Journal of Agricultural and Forest Meteorology
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• v.23 no.1
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• pp.15-33
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• 2021

In this study, the possibility of discriminating Fire blight (FB) infection tested using the hyperspectral imagery. The reflectance of healthy and infected leaves and branches was acquired with 5 nm of full width at high maximum (FWHM) and then it was standardized to 10 nm, 25 nm, 50 nm, and 80 nm of FWHM. The standardized samples were divided into training and test sets at ratios of 7:3, 5:5 and 3:7 to find the optimal bands of FWHM by the decision tree analysis. Classification accuracy was evaluated using overall accuracy (OA) and kappa coefficient (KC). The hyperspectral reflectance of infected leaves and branches was significantly lower than those of healthy green, red-edge (RE) and near infrared (NIR) regions. The bands selected for the first node were generally 750 and 800 nm; these were used to identify the infection of leaves and branches, respectively. The accuracy of the classifier was higher in the 7:3 ratio. Four bands with 50 nm of FWHM (450, 650, 750, and 950 nm) might be reasonable because the difference in the recalculated accuracy between 8 bands with 10 nm of FWHM (440, 580, 640, 660, 680, 710, 730, and 740 nm) and 4 bands was only 1.8% for OA and 4.1% for KC, respectively. Finally, adding two bands (550 nm and 800 nm with 25 nm of FWHM) in four bands with 50 nm of FWHM have been proposed to improve the usability of multispectral image sensors with performing various roles in agriculture as well as detecting FB with other combinations of spectral bands.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.562-565
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• 2001

In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.777-779
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• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Food Science and Preservation
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• v.22 no.4
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• pp.553-558
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• 2015

The aims of this study was to optimize the extraction conditions of sinigrin from Dolsan leaf mustard. Dolsan leaf mustard (Dolsan-eup, Yeosu-si) harvested during at May 2014 was used for sinigrin extraction. After the extraction of sinigrin using 50% $CH_3CN$, 10% $NH_4Cl$, 60% $CH_2OH$, and 70% $CH_3OH$, the sinigrin content was measured by HPLC analysis. The results showed that sinigrin content was highest with 50% $CH_3CN$ solvent extraction and UV detector sensitivity was greater at 228 nm rather than at 242 nm. The sinigrin concentrations of leaf, stem and root with 50% $CH_3CN$ extraction were 345 ppm, 728 ppm, and 539 ppm, respectively. After extraction of the different parts of Dolsan leaf mustard, The standard retention time by HPLC analysis of sinigrin content was 2.054, 2.032, 2.059, and 2.035 min from the root, stalk, and leaf, respectively. On the other hand, HPLC analysis showed that the leaf extracts contained glucoraphanin, one of glucosinolates. The optimum time and extraction solvent for the sinigrin extraction from Dolsan leaf mustard was found to be 24 hr with 50% $CH_3CN$ solvent. In addition, opotimum UV detector k at 228 nm. These results showed that the optimum extraction conditions for Dolsan leaf mustard were 24 hr extraction with 50% $CH_3CN$ solvent. In addition, the optimum wavelength of UV detector was determined to be 228 nm for sinigrin analysis. Therefore, this study could provide a useful information for sinigrin extraction and its systematic analysis during the storage.

• Applied Microscopy
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• v.29 no.3
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• pp.265-274
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• 1999

The microstructure of Cu thin films in various deposition conditions was characterized. Cr films (50 nm thick) and Cu films (500 or 1000 nm thick) were deposited on polyimide films by DC magnetron sputtering. The Ar pressure during Cu deposition was controlled to 5, 50 and 100 mtorr. The microstructure was characterized using conventional and high resolution SEM and TEM. As sputtering pressure increases, open boundaries are observed more frequently. The Cu film deposited at 5 mtorr has a dense and uniform structure, while low-density regions or open boundaries between columns exist in the film deposited at higher pressure. As the film grows thicker, open boundaries are wider and the density of open boundaries are higher. The comparison between SEM and TEM show that the small features shown in high resolution SEM are grains. High resolution SEM is very effective to characterize the microstructure of the thin films. One column in the films deposited at 50 and 100 mtorr consists of several grains, which are smaller than those deposited at 5 mtorr.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.486-489
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• 2002

In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

• Polymer Science and Technology
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• v.15 no.3
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• pp.303-316
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• 2004

균일한 크기의 미세 기공이 규칙적으로 배열되어 있는 다공성 분자체 물질 (porous molecular sieve materials)은 분자 단계의 물질들을 선택적으로 분리 흡착할 수 있는 장점을 가지고 있으며, 이를 이용하여 다양한 화학 반응의 촉매 및 촉매의 담체로서 널리 사용되어 왔다. 미세 기공 물질은 IUPAC 정의에 따르면 세공의 크기에 따라 기공의 직경이 1.5 nm 미만인 마이크로포러스 물질 (microporous materials), 1.5 nm 이상 50 nm 미만의 메조포러스 물질(mesoporous materials), 그리고 50 nm 이상의 매크로포러스 물질 (macroporous materials)로 나누어진다. (중략)

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.259-259
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• 2016

반도체 산업 전반에 걸쳐 이루어지고 있는 연구는 소자를 더 작게 만들면서도 구동능력은 우수한 소자를 만들어내는 것이라고 할 수 있다. 따라서 소자의 미세화와 함께 트랜지스터의 구동능력의 향상을 위한 기술개발에 대한 필요성이 점차 커지고 있으며, 고유전(high-k)재료를 트랜지스터의 게이트 절연막으로 이용하는 방법이 개발되고 있다. High-k 재료를 트랜지스터의 게이트 절연막에 적용하면 낮은 전압으로 소자를 구동할 수 있어서 소비전력이 감소하고 소자의 미세화 측면에서도 매우 유리하다. 그러나, 초미세화된 소자를 제작하기 위하여 high-k 절연막의 두께를 줄이게 되면, 전기적 용량(capacitance)은 커지지만 에너지 밴드 오프셋(band-offset)이 기존의 실리콘 산화막(SiO2)보다 작고 또한 열공정에 의해 쉽게 결정화가 이루어지기 때문에 누설전류가 발생하여 소자의 열화를 초래할 수 있다. 따라서, 최근에는 이러한 문제를 해결하기 위하여 게이트 절연막 엔지니어링을 통해서 누설전류를 줄이면서 전기적 용량을 확보할 수 있는 연구가 주목받고 있다. 본 실험에서는 high-k 물질인 Ta2O5와 SiO2를 적층시켜서 누설전류를 줄이면서 동시에 높은 캐패시턴스를 달성할 수 있는 게이트 절연막 엔지니어링에 대한 연구를 진행하였다. 먼저 n-type Si 기판을 표준 RCA 세정한 다음, RF sputter를 사용하여 두께가 Ta2O5/SiO2 = 50/0, 50/5, 50/10, 25/10, 25/5 nm인 적층구조의 게이트 절연막을 형성하였다. 다음으로 Al 게이트 전극을 150 nm의 두께로 증착한 다음, 전기적 특성 개선을 위하여 furnace N2 분위기에서 $400^{\circ}C$로 30분간 후속 열처리를 진행하여 MOS capacitor 소자를 제작하였고, I-V 및 C-V 측정을 통하여 형성된 게이트 절연막의 전기적 특성을 평가하였다. 그 결과, Ta2O5/SiO2 = 50/0, 50/5, 50/10 nm인 게이트 절연막들은 누설전류는 낮지만, 큰 용량을 얻을 수 없었다. 한편, Ta2O5/SiO2 = 25/10, 25/5 nm의 조합에서는 충분한 용량을 확보할 수 있었다. 적층된 게이트 절연막의 유전상수는 25/5 nm, 25/10 nm 각각 8.3, 7.6으로 비슷하였지만, 문턱치 전압(VTH)은 각각 -0.64 V, -0.18 V로 25/10 nm가 0 V에 보다 근접한 값을 나타내었다. 한편, 누설전류는 25/10 nm가 25/5 nm보다 약 20 nA (@5 V) 낮은 것을 확인할 수 있었으며 절연파괴전압(breakdown voltage)도 증가한 것을 확인하였다. 결론적으로 Ta2O5/SiO2 적층 절연막의 두께가 25nm/10nm에서 최적의 특성을 얻을 수 있었으며, 본 실험과 같이 게이트 절연막 엔지니어링을 통하여 효과적으로 누설전류를 줄이고 게이트 용량을 증가시킴으로써 고집적화된 소자의 제작에 유용한 기술로 기대된다.

• Resources Recycling
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• v.16 no.1 s.75
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• pp.28-36
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• 2007

Nano-sized ITO powders with the average particle size below 50 nm were synthesized from complex acid solution dissolved the ITO target into hydrochloric acid by a spray pyrolysis process, and the influences of reaction factors as reaction temperature and concentration of raw material solution were investigated. As the reaction temperature increases from 800 to $1000^{\circ}C$, the average particle size of the ITO powder increases from 40 nm to 100 nm, the microstructure gradually becomes solid, individual particles independently appear with the shape of polygon, the particle size distribution becomes increasingly irregular, the XRD peak intensity gradually increases and the specific surface area decreases. As the concentration of the raw material solution increases from 50g/l to 400g/l, the average particle size of ITO powder gradually increases, yet the particle size distribution appears more irregular. When the concentration is at 50 g/l, the average particle size of ITO powder is below 30 nm and the particle size distribution appears comparatively uniform. Nevertheless, when the concentration reaches 400 g/l, which is close to e saturated concentration, the particle size distribution appears extremely irregular, and the particles with the size ranging from 20 nm to 100 nm coexist. Along with the concentration rise, the XRD peak intensity gradually increases, yet the specific surface area decreases.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.