• Title/Summary/Keyword: 5.8 GHz

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Broadband LTCC Receiver Module for Fixed Communication in 40 GHz Band (40 GHz 대역 고정통신용 광대역 LTCC 수신기 모듈)

  • Kim Bong-Su;Kim Kwang-Seon;Eun Ki-Chan;Byun Woo-Jin;Song Myung-Sun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.10 s.101
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    • pp.1050-1058
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    • 2005
  • This paper presents how to design and implement a very compact, cost effective and broad band receiver module for IEEE 802.16 FWA(Fixed Wireless Access) in the 40 GHz band. The presented receiver module is fabricated in a multi-layer LTCC(Low Temperature Cofired Ceramic) technology with cavity process to achieve excellent electrical performances. The receiver consists of two MMICs, low noise amplifier and sub-harmonic mixer, an embedded image rejection filter and an IF amplifier. CB-CPW, stripline, several bond wires and various transitions to connect each element are optimally designed to keep transmission loss low and module compact in size. The LTCC is composed of 6 layers of Dupont DP-943 with relative permittivity of 7.1. The thickness of each layer is 100 um. The implemented module is $20{\times}7.5{\times}1.5\;mm^3$ in size and shows an overall noise figure of 4.8 dB, an overall down conversion gain of 19.83 dB, input P1 dB of -22.8 dBm and image rejection value of 36.6 dBc. Furthermore, experimental results demonstrate that the receiver module is suitable for detection of Digital TV signal transmitted after up-conversion of $560\~590\;MHz$ band to 40 GHz.

Design of Wideband Bow-Tie Antenna with Folded-Slit Band-Notch Structure (폴디드 슬릿 대역저지 구조를 적용한 광대역 보우타이 안테나 설계)

  • Nam, Hyun-Soo;Woo, Dong Sik;Kim, Sung-Kyun;Kim, In-Bok;Choi, Hyun-Chul;Kim, Kang Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.9
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    • pp.886-894
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    • 2014
  • A wideband bow-tie antenna fed by wideband microstrip-coplanar stripline(CPS) balun and band notch structures that can be applied to bow-tie antenna are proposed in this paper. In order to increase bandwidth, bow-tie radiators are reshaped so that the surface current flows continuously, and wideband impedance matching is achieved by adjusting strip width and spacing of CPS feeding line. The VSWR is measured as 2:1 over the wide frequency range of 2.3~12 GHz. The fabricated antenna size is $60mm{\times}60mm$. In order to achieve the band-notch function at WLAN(5.8 GHz), ${\lambda}/4$ folded-slits located ${\lambda}/4$ away from feeding point are utilized. To minimize the slit size, folded-slit type is adopted. The measured VSWR is 7:1 and gain attenuation is 14 dB at 5.8 GHz.

High Gain and Broadband SAP Antenna with Two Parasitic Patches (두 개의 기생 패치를 갖는 고 이득.광대역 SAP 안테나)

  • Kim, Jung-Han;Kim, Yong-Jin;Lee, Hong-Min
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.930-936
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    • 2007
  • In this paper, the high gain and broadband antenna operating for SDMB(Satellite Digital Multimedia Broadcasting) system is realized, The proposed antenna consists of the SAP(Shorted Annular Patch) structure, which inhibits surface-wave and the parasitic SAP element with spacing of $0.25 {\lambda}_0$ in order to improve gain, bandwidth and directivity. The RHCP(Right Hand Circular Polarization) is generated by two slits, which are made along the periphery of the circular patch at the diametrically opposite points, The simulated maximum gain of the proposed antenna is 12.6 dBi, which is better 5.22 dBi than maximum gain of the conventional microstrip patch antenna. The measured maximum gain is 10.5dBi at operating frequency 2.63GHz. Also, the measured impedance bandwidth$(VSWR{\leq}2)$ of the proposed antenna is $360MHz(2.488{\sim}2.848 GHz)$, which is better 300 MHz than the bandwidth of the conventional microstrip patch antenna. The measured HPBW(Half Power Beam Width) of the proposed antenna is $45.8^{\circ}$, and the measured FBR(Front to Back Ratio) is 15.49 dBi, The 3dB axial ratio bandwidth is 220 MHz$(2.54{\sim}2.76 GHz)$.

Design of Single Balanced Diode Mixer with Filter for Improving Band Flatness in Microwave Frequency Down Converter (마이크로파 주파수 하향 변환기에서의 대역 평탄도 개선을 위한 여파기 집적형 단일 평형 다이오드 혼합기 설계)

  • Ryu, Seung-Kab;Hwang, In-Ho;Han, Seok-Kyun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.1 s.116
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    • pp.37-43
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    • 2007
  • In this.paper, we introduce design and implementation results of the single balanced diode mixer for European point-to-point microwave radio in order to improve flatness performance. When a resonator such as RF filter is integrated with a mixer, impedance characteristic of 50 ohm is maintained only in RF band, not in LO band resulting deterioration of flatness performance because of LO power variation on the diode. In the paper, we suggest a design method of mixer integrated with image rejection filter and LO harmonic filter to have a better performance of flatness using embedding electrical length between filter and mixer's port. Frequency specification of fabricated mixer is $21.2{\sim}22.6\;GHz$ for RF, $19.32{\sim}20.72\;GHz$ for LO and 1.88 GHz+/-50 MHz for IF, respectively. Measured results show conversion loss of 8.5 dB, flatness of 2 dB, input PldB of 8 dBm, IIP3 of 15 dBm under LO power level of 10 dBm. Return losses of RF, LO and IF port are under -12 dB, -10 dB and -5 dB, respectively. Isolations of LO/RF and LO/IF are 20 dB and 50 dB, respectively.

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

  • Misra, Prasanna Kumar;Qureshi, S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.274-283
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    • 2014
  • In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

INTRINSIC BRIGHTNESS TEMPERATURE OF COMPACT RADIO SOURCES AT 86GHZ

  • Lee, Sang-Sung
    • Journal of The Korean Astronomical Society
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    • v.46 no.6
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    • pp.243-251
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    • 2013
  • We present results on the intrinsic brightness temperature of a sample of compact radio sources observed at 86 GHz using the Global Millimeter VLBI Array. We use the observed brightness temperatures at 86 GHz and the observed superluminal motions at 15 GHz for the sample in order to constrain the characteristic intrinsic brightness temperature of the sample. With a statistical method for studying the intrinsic brightness temperatures of innermost jet cores of compact radio sources, assuming that all sources have the same intrinsic brightness temperature and the viewing angles of their jets are around the critical value for the maximal apparent speed, we find that sources in the sample have a characteristic intrinsic brightness temperature, $T_0=4.8^{+2.6}_{-1.5}{\times}10^9K$, which is lower than the equipartition temperature for the condition that the particle energy equals to the magnetic field energy. Our results suggest that the VLBI cores seen at 86 GHz may be representing a jet region where the magnetic field energy dominates the total energy in the jet.

Diversity characteristics of four-element ring slot-based MIMO antenna for sub-6-GHz applications

  • Vipul Kaushal;Amit Birwal;Kamlesh Patel
    • ETRI Journal
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    • v.45 no.4
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    • pp.581-593
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    • 2023
  • This paper proposes four-ring slot resonator-based MIMO antennas of 75×150 mm2 without and with CSRR structures in the sub-6-GHz range. These orthogonal-fed antennas have shown diverse characteristics with dual polarization. L-shaped parasitic structures have increased the isolation (i.e., >40 dB) in the single-element antenna over the band of 3.4 GHz-3.8 GHz. A set of three CSRR structures in the MIMO antenna reduced the coupling between antenna ports placed in an inline arrangement and enhanced the isolation from 12 dB to 20 dB and the diversity characteristics. The S-parameters of both MIMO antennas are measured and used to evaluate MIMO parameters like ECC, TARC, MEG, and channel capacity loss. The simulation results show the variations in the gain and directivity on exciting linear and dual polarizations. The diversity performance of the reported MIMO antennas is suitable for 5G applications.

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

  • Noh, Youn-Sub;Chang, Dong-Pil;Yom, In-Bok
    • ETRI Journal
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    • v.31 no.3
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    • pp.247-253
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    • 2009
  • We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 ${\mu}m$ GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.

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A High-Resolution Dual-Loop Digital DLL

  • Kim, Jongsun;Han, Sang-woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.4
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    • pp.520-527
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    • 2016
  • A new dual-loop digital delay-locked loop (DLL) using a hybrid (binary + sequential) search algorithm is presented to achieve both wide-range operation and high delay resolution. A new phase-interpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a $0.18-{\mu}m$ CMOS process, occupies an active area of $0.19mm^2$ and operates over a wide frequency range of 0.15-1.5 GHz. The DLL dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps (effective pk-pk jitter = 16.5 ps) with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps.

Spectrum Access Model Proposal for Frequency Sharing in 3~4 GHz (3~4 GHz 대 주파수 공동사용을 위한 스펙트럼 액세스 모델 제안)

  • Kang, Young-Heung;Lee, Dae-Young;Park, Duk-Kyu
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.8
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    • pp.821-827
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    • 2014
  • Many researches on the usage of shared spectrum have continuously been carried out to solve the recent frequency shortage problem and to use efficiently the spectrum without interference. Also, exponential mobile data growth and the solutions needed to address this challenge are parallel key objectives addressed in many countries. Spectrum policy innovation to meet this challenge is the ASA/LSA (Authorized Shared Access/Licensed Shared Access), which is the best access model to employ the small cell technology to meet this mobile traffic growth. Because 3.5 GHz bands is considered as the ASA/LSA frequency, in this paper, we propose the SAM(Spectrum Access Model) in 3~4 GHz bands to estimate the available ASA/LSA bands and to open more free spectrum. These results are utilized as the data to develop the SAM for the small cell and the open frequency in future.