• Title/Summary/Keyword: 5.25-GHz

Search Result 449, Processing Time 0.023 seconds

Design of Active Antenna Diplexers Using UWB Planar Monopole Antennas (초광대역 평면형 모노폴 안테나를 이용한 능동 안테나 다이플렉서의 설계)

  • Kim, Joon-Il;Lee, Won-Taek;Chang, Jin-Woo;Jee, Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.18 no.9
    • /
    • pp.1098-1106
    • /
    • 2007
  • This paper presents active antenna diplexers implemented into an ultra-wideband CPW(Coplanar Waveguide) fed monopole antennas. The proposed active antenna diplexer is designed to direct interconnect the output port of a wideband antenna to the input port of two active(HEMT) devices, where the impedance matching conditions of the proposed active integrated antenna are optimized by adjusting CPW(Coplanar Waveguide) feed line to be the length of 1/20 $\lambda_0$(@5.8 GHz) in planar type wideband antenna. The measured bandwidth of the active integrated antenna shows the range from 2.0 GHz to 3.1 GHz and from 5.25 GHz to 5.9 GHz. The measured peak gains are 17.0 dB at 2.4 GHz and 15.0 dB at 5.5 GHz.

An UWB Design of Plane Bow-Tie Monopole Antenna (평면형 보우타이 모노폴 안테나의 초광대역 설계)

  • Kim, Tae-Woo;Choi, Kyoung;Hwang, Hee-Yong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.25 no.12
    • /
    • pp.1212-1218
    • /
    • 2014
  • This paper proposes a planar bow-tie UWB antenna by modifying the ground patch of a reference bowtie-monopole antenna satisfying low band of UWB. The proposed antenna was implemented with five-angled ground patch to be operated in whole UWB band, while the reference antenna had a ground patch of half circle type. The measured return loss satisfies less than -10 dB in 3.1~10.6 GHz, except 4.9~5.8 GHz rejection band. The measured radiation pattern is almost the same with that of the monopole antenna. The radiation gain reduction is about 8 dB at rejection band.

Design of a New RF Built-In Self-Test Circuit for 5.25GHz SiGe Low Noise Amplifier (5.25GHz 저잡음 증폭기를 위한 새로운 고주파 BIST 회로 설계)

  • 류지열;노석호;박세현;박세훈;이정환
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2004.05b
    • /
    • pp.635-641
    • /
    • 2004
  • This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHa low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

  • PDF

Realization of a 7.7~8.5GHz 10 W Solid-State Power Amplifier (7.7~8.5 GHz 10 W 반도체 전력 증폭기의 구현에 관한 연구)

  • 박효달;김용구
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.19 no.12
    • /
    • pp.2489-2497
    • /
    • 1994
  • This paper presents the development of a 10 W solid-state hybrid power amplifier(SSPA). operating over $7.7\sim8.5GHz$. The fabrication and measurement of this amplifier are performed with 3 sections, such as the front one for high gain, the middle one for driving, and high power one, to minimize the risk of failure and to increase the easiness of development. and then the final amplifier is realized by connecting 3 sections above mentioned, DC bias circuit, and temperature compensation circuit on one housing. Total small signal gain obtained is about $45\pm1dB$, the input and output return losses are 25 and 27 dB respectively. The output power measured at 1 dB gain compression point for 3 frequencies at 7.7, 8.1, and 8.5 GHz are $39.8\sim40.4dBm$, which is about 10 W. and the 3rd-order harmonic powers of 2 tones test are 13.34 dBc at output power 37.5 dBm. These obtained results satisfies the initially required specification. and the realized SSPA can be installed as a subsystem of the microwave transponder for telecommunication.

  • PDF

Design and Fabrication of a Active Resonator Oscillator using Active Inductor and Active Capacitor with Negative Resistance (부성저항 특성을 갖는 능동 인덕터와 능동 캐패시터를 이용한 능동 공진 발진기 설계 및 제작)

  • 신용환;임영석
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.7 no.8
    • /
    • pp.1591-1597
    • /
    • 2003
  • In this paper, Active Resonator Oscillator using active inductor and active capacitor with HEMTs(agilent ATF­34143) is designed and fabricated. Active inductor with ­25$\Omega$ and 2.4nH in 5.5GHz frequency band and Active capacitor with ­14$\Omega$ and 0.35pF is designed. Active Resonator Oscillator for LO in ISM band(5.8GHz) is designed with active inductor and active capacitor. Active Resonator Oscillator has been simulated by Agilent ADS 2002C. Active Resonator oscillator implemented on the substrate which has the relative dielectric constant of 3.38, the height of 0.508mm, and metal thickness of 0.018mm. This Active Resonator Oscillator shows the oscillation frequency of 5.68GHz with the output power of ­3.6㏈m and phase noise of ­81㏈c/Hz at the offset frequency of 100KHz.

A 3~5 GHz Interferer Robust IR-UWB RF Transceiver for Data Communication and RTLS Applications (간섭 신호에 강인한 특성을 갖는 데이터 통신과 위치 인식 시스템을 위한 3~5 GHz 대역의 IR-UWB RF 송수신기)

  • Ha, Jong Ok;Park, Myung Chul;Jung, Seung Hwan;Eo, Yun Seong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.25 no.1
    • /
    • pp.70-75
    • /
    • 2014
  • This paper presents a IR-UWB(Impulse Radio Ultra-Wide Band) transceiver circuit for data communication and real time location system. The UWB receiver is designed to OOK(On-Off Keying) modulation for energy detection. The UWB pulse generator is designed by digital logic. And the Gaussian filter is adopted to reject side lobe in transmitter. The measured sensitivity of the receiver is -65 dBm at 4 GHz with 1 Mbps PRF(Pulse Repetition Frequency). And the measured energy efficiency per pulse is 20.6 pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5 mA and 25.5 mA, respectively, at 1.8 V supply.

Design of Variable Gain Receiver Front-end with Wide Gain Variable Range and Low Power Consumption for 5.25 GHz (5.25 GHz에서 넓은 이득 제어 범위를 갖는 저전력 가변 이득 프론트-엔드 설계)

  • Ahn, Young-Bin;Jeong, Ji-Chai
    • Journal of IKEEE
    • /
    • v.14 no.4
    • /
    • pp.257-262
    • /
    • 2010
  • We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

Design and fabrication of multilayer LTCC BPF using DGS structure (DGS 구조를 이용한 적층 LTCC 대역통과 필터의 설계 및 제작)

  • Cho, Y.K.;Kim, H.S.;Song, H.S.;Park, K.H.
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
    • /
    • 2003.11a
    • /
    • pp.333-337
    • /
    • 2003
  • In this paper, 5.2 GHz WLAN BPF(Band Pass Filter) using LTCC(Low temperature co-firing ceramic) Multilayer technology was simulated and manufactured. A DGS(Defected Ground structure) resonator with spiral ground pattern is used to shorten resonator size and improve circuit Q factor. And the equivalent circuit of BPF was suggested. The measured result shows good agreement with simulated data. Experimental results show the center frequency of 5.25GHz, the insertion loss of 0.14dB, and the 3-dB bandwidth of 350MHz (6%). The center frequency of BPF is 5.25GHz which is available for wireless LAN.

  • PDF

A Reconfigurable CMOS Power Amplifier for Multi-standard Applications (다양한 표준에서 사용 가능한 CMOS 전력 증폭기)

  • Yun, Seok-Oh;Yoo, Hyung-Joun
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.11
    • /
    • pp.89-94
    • /
    • 2007
  • For successful implementation of multi-standard transmitter, reconfigurable architecture and component design are essential. This paper presents a reconfigurable CMOS power amplifier designed CMOS 0.25 um process. Designed power amplifier can be operated at 0.9, 1.2, 1.75, and 1.85 GHz. Also, it can be used at 2.4 GHz by using bonding wire inductor. The interstage matching network is composed of two inductors and four switches, and operation frequency can be varied by controlling switches. Proposed power amplifier can be used as a power amplifier in low power applications such as ZigBee or Bluetooth application and used as a driver amplifier in high power application such as CDMA application. Designed power amplifier has 18.2 dB gain and 10.3 dBm output power at 0.9 GHz. Also, it represented 10.3 (18.1) dB gain and 5.2 (10) dBm output power at 1.75 (2.4) GHz.

Design of a New RF Buit-In Self-Test Circuit for Measuring 5GHz Low Noise Amplifier Specifications (5GHz 저잡음 증폭기의 성능검사를 위한 새로운 고주파 Built-In Self-Test 회로 설계)

  • Ryu Jee-Youl;Noh Seok-Ho;Park Se-Hyun
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.8 no.8
    • /
    • pp.1705-1712
    • /
    • 2004
  • This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.