• Journal of the Korea institute for structural maintenance and inspection
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• v.7 no.2
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• pp.177-184
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• 2003

A series of experimental work has been conducted to evaluate the capability of Ground Penetrating Radar (GPR) system in detecting delamination inside concrete. Three antenna at 900 MHz, 1000 MHz, and 1500 MHz frequency are used in the experiments for laboratory size specimens, and 400 MHz antenna has been used for a large size specimen. The laboratory size specimens have the dimensions of 1,000 mm (length) ${\times}$ 600 mm (width) ${\times}$ 140 mm (thickness) with a delamination of 200 mm (length) ${\times}$ 600 mm (width) ${\times}$ 140 mm (thickness). The cover depth of the delamination is varied as follows: 20 mm, 30 mm, 60 mm, and 70 mm. In all cases, the delamination has been successfully identified. The property of three frequencies was seized about detecting delamination. Also, it was shown that the image results in GPR were improved by signal processing.

• Journal of Internet Computing and Services
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• v.10 no.1
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• pp.1-9
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• 2009

In this paper, A pipeline structured-degree computationless modified Euclidean (PS-DCME) algorithm is proposed, which can be used for a RS(23,17) decoder for MB-OFDM system. PS-DCME algorithm requires a state machine instead of the degree computation and comparison circuits, so that the hardware complexity of the decoder can be reduced and high-speed decoder can be implemented. We have implemented a RS(23,17) decoder with PS-DCME using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 19,827.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Journal of the Korean Society for Heat Treatment
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• v.8 no.3
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• pp.182-186
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• 1995

SCM440, which is widely used as the diesel engine piston of vessel, has been hardened by a $CO_2$ laser with the wavelength of $10.6{\mu}m$. Laser hardening experiment has been carried out for the condition of a laser power 1kW, the travel speed between 0.4 and 1.5m/min, and a rectangular-Gaussian beam. Residual stress has been measured by using middle point technique of half value width of X-ray diffraction method. It was found that the compressive residual stress with the range between 400 and 600MHz has distributed in the laser hardening zones and the tensile residual stress between 100 and 200MHz has distributed in the boundary of hardening zones.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.485-489
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• 2000

본 논문에서는 단일 PLL을 사용하여 400MHz 대역의 트랜시버를 구현하였다. 일반적인 트랜시버의 경우, 송수신부에 각각 한 개의 PLL과 수신부에 2단의 믹서를 사용하여 구현되어진다. 이러한 구성은 트랜시버의 가격과, 부피에 상당히 큰 영향을 미친다. 본 논문에서는 기존의 방식을 탈피하여 단일 PLL방식의 데이터 전송용 특정 소출력 무선기기의 송, 수신단의 회로설계, 제작 및 특성측정을 하였다. 설계된 트랜시버의 주파수 대역은 424.7-424.95MHz이고, Low Side Injection방식을 사용하여 450KHz의 If 주파수로 변환(Conversion)하였고, 반이중(Semi duplex Communication) 통신방식, PLL Synthesized, 21 Channel, 12.5KHz Channel BandwidttL FSK Modulation / Demodulation 방식을 사용하였다.

• Proceedings of the KIEE Conference
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• 2005.11b
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• pp.322-324
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• 2005

This paper describes the comparison of Two frequency ranges for power line communication. The first one is that the frequency range from 100 to 400 KHz is supported by the Federal Communication Committee(FCC). The other one is that the frequency range from 1MHz to 30MHz is based on the European-supported EN5006A band. In this paper, the advantages and disadvantages of their frequency ranges are discussed for PLC. By ATP/EMTP software, the signal attenuation is simulated both the frequency ranges. It shows that the signal attenuation is bigger at high frequency than at low frequency.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.330-333
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• 2003

본 논문에서는 조립/제작, 시험과정을 통하여 개발된 통신방송위성용 Ka 대역 통신위성 중계기의 구조 및 성능에 대하여 기술한다. 개발된 중계기는 전체 400MHz 대역 내에 100 MHz 대역폭을 갖는 3 개의 통신채널을 수용하여 광대역 멀티미디어 서비스를 지원할 수 있도록 설계되었으며 국내 기술로 제작되어 우주인증을 거친 IFA, RxDC, IMUX, CH-AMP 등의 부품으로 구성되어 있다. 중계기에 대한 성능시험은 EGSE를 이용해 자동으로 수행되었으며, 성능시험결과 대부분의 성능 항목이 요구사항과 부합됨을 확인하였다. 제작된 Ka 대역 중계기에 적용된 위성 중계기 및 부품의 제작 및 시험 기술은 향후 통신해양기상위성에 탑재될 중계기의 개발에 직접 응용이 가능하다.

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Electrical & Electronic Materials
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• v.10 no.8
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• pp.813-818
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• 1997

In this study the thin film air core and magnetic core inductors consisting of planar coil and/or CoNbZr amorphous magnetic layers on a Si substrate were fabricated as spiral type by using rf magnetron sputtering and wet etching methods. The etchant solution was achieved by iron chloride solution(17.5 mol%) mixed with HF (20 mol%) during 150 sec which etched Cu films and CoNbZr/Cu/CoNbZr multi-layer films. They were about 10${\mu}{\textrm}{m}$ of thickness and 10$\times$10 mm$^2$of size. The properties of thin film magnetic core inductor were 400 nH of Q value at 10 MHz and the resonance frequency was about 300 MHz.