• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.96-103
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• 2008

This paper proposes a new low-power and small-area Reed-Solomon decoder. The proposed Reed-Solomon decoder using a novel simplified form of the modified Euclid's algorithm can support low-hardware complexity and low-Power consumption for Reed-Solomon decoding. The simplified modified Euclid's algorithm uses new initial conditions and polynomial computations to reduce hardware complexity, and thus, the implemented architecture consisting of 3r basic cells has the lowest hardware complexity compared with existing modified Euclid's and Berlekamp-Massey architectures. The Reed-Solomon decoder has been synthesized using the $0.18{\mu}m$ Samsung standard cell library and operates at 370MHz and its data rate supports up to 2.9Gbps. For the (255, 239, 8) RS code, the gate counts of the simplified modified Euclid's architecture and the whole decoder excluding FIFO memory are only 20,166 and 40,136, respectively. Therefore, the proposed decoder can reduce the total gate count at least 5% compared with the conventional DCME decoder.

• Korean Journal of Optics and Photonics
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• v.5 no.1
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• pp.113-119
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• 1994

We fabricated and characterized RWG-DFB-LDs emitting at $1.3\mu\textrm{m}$ wavelength. For fabrication of the laser diode, inteference fringe of optical beams was used for grating formation and epi layers were grown by LPE. The fablicated RWG-DFB-LD operated in a single longitudinal mode with more than 30 dB SMSR at 1296.5 nm emitting wavelength and its threshold current was 67 mA. Coupling coefficient (K) was estimated as $40cm^{-1}$ by means of stop-band measurement. Finally, we show that the RWG-DFB-LD fabricated in this experiment can be applicable as light source of 2.5 Gbps optical communication system from the fact that the small signal response of the RWG-DFB-LD rated up to 1.99 GHz at pre-bias level of $1.2 I_{th}$..

• Journal of Advanced Navigation Technology
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• v.11 no.2
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• pp.177-186
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• 2007

In this paper, the optimal position offset of optical phase conjugator (OPC) and the optimal dispersion offsets of fiber sections, which are alternating with the method for the symmetry of optical power and chromatic dispersion with respect to OPC, are numerically investigated as afunction of the WDM channel numbers. The WDM channel numbers are assumed to be 8, 12, 16, 20 and 24. The bit-rate of each channel is assumed to be 40 Gbps for all cases. It is confirmed that the optimal position offset of OPC and optimal dispersion offset of fiber section are gradually increased as the WDM channel numbers are gradually increased. But, the optimal dispersion values of fiber sections per OPC position offset of 1 km are independent on WDM channel numbers, because the optimal position offset of OPC and optimal dispersion offset of fiber section are simultaneously increased as the WDM channel numbers are increased. It is also confirmed that the applying of these optimal parameter values is efficient to WDM system with many channels rather than WDM with small channels.

• Journal of Advanced Navigation Technology
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• v.11 no.2
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• pp.187-195
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• 2007

In this paper, the optimal values of optical phase conjugator (OPC) position and dispersion coefficients of fiber sections depending on the extinction ratio of WDM channel signals are numerically induced in WDM system with OPC used to compensate the distorted signals due to nonlinearities and chromatic dispersion. The considered WDM system consist of 16 channels with 40 Gbps data rate and each channel is assumed to be NRZ format with the extinction ration of 5 dB, 10 dB, or 20 dB. It is confirmed that the only one parameter among two considered parameters is used to effectively compensate overall WDM channels, and each optimal value of these parameters independent on the extinction ratio. That is, overall WDM channels are excellently transmitted within 2 dB power penalty whether by positioning OPC into 496 km or by setting dispersion coefficient difference between two fiber sections to 0.055 ps/nm/km, these optimal values are not dependence on the extinction ratio.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.619-626
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• 2004

In this paper, we investigated the compensation characteristics of distorted 16-channel WDM signal due to chromatic dispersion self phase modulation(SPM) and four-wave mixing(FWM). The bit rate and uniform frequency spacing of WDM channels are assumed to be 40 Gbps and 100 ㎓, respectively. The compensation method used in this approach is mid- span spectral inversion(MSSI), Highly-nonlinear dispersion shifted fiber(HNL-DSF) is used as a nonlinear medium of optical phase conjugator(On) in order to widely compensate WDM signal band. We confirmed that applying MSSI in WDM channels within special input power level compensates overall interferenced channels mainly due to FWM. But for long wavelength WDM channels having lower conjugated light power with respect to signal light power, compensation quality is deteriorated as dispersion coefficient of fiber becomes higher. Consequently, we confirmed that it is effective D apply MSSI with HNL-DSF as a nonlinear medium of OPC to WDM transmission link with relative small dispersion in order to compensate equally spaced WDM channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.1
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• pp.51-57
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• 2016

This paper describes the physical layer modem structure of Giga KOREA 5G system which is being developed by ETRI as a 5G telecommunications prototype. The objective of Giga KOREA 5G system is supporting maximum 100 Gbps data rate for each cell with wide-bandwidth baseband station and mobile station prototypes in mmWave (10~40 GHz) environment. To achieve this objective, its physical layer is composed of high performance baseband station as well as mobile station and their OFDM TDD modems. The important features of Giga KOREA 5G physical layer are carrier aggregation, multiple receiving beam searching in mobile station, high data rate channel encoder and decoder and high speed modulation and demodulation functions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.19-24
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• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.